Chapter 41 gmac ethernet Interface



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Bit

Attr

Reset Value

Description

31:0


RW


0x00000000



HTH
Hash Table High
This field contains the upper 32 bits of Hash table



GMAC_HASH_TAB_LO


Address: Operational Base + offset (0x000c) Hash Table Low Register

Bit

Attr

Reset Value

Description

31:0


RW


0x00000000



HTL
Hash Table Low
This field contains the lower 32 bits of Hash table



GMAC_GMII_ADDR



Only

T-chip
Address: Operational Base + offset (0x0010) GMII Address Register

Bit

Attr

Reset Value

Description

31:16

RO

0x0

reserved

15:11


RW


0x00


PA
Physical Layer Address
This field tells which of the 32 possible PHY devices are being accessed

10:6


RW


0x00


GR
GMII Register
These bits select the desired GMII register in the selected PHY device


Only

T-chip



Bit

Attr

Reset Value

Description

5:2


RW


0x0


CR
APB Clock Range
The APB Clock Range selection determines the frequency of the MDC clock as per the pclk_gmac frequency used in your design. The suggested range of pclk_gmac frequency applicable for each value below (when Bit[5]
= 0) ensures that the MDC clock is approximately between the frequency range
1.0 MHz - 2.5 MHz.
Selection pclk_gmac MDC Clock 0000 60-100 MHz
pclk_gmac/42
0001 100-150 MHz
pclk_gmac/62
0010 20-35 MHz
pclk_gmac/16
0011 35-60 MHz
pclk_gmac/26
0100 150-250 MHz
pclk_gmac/102
0101 250-300 MHz
pclk_gmac/124
0110, 0111 Reserved
When bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE
802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower
value. For example, when pclk_gmac is of frequency 100 Mhz and you program these bits as "1010", then the resultant MDC clock will be of 12.5 Mhz which is outside the limit of IEEE 802.3 specified range. Please program the values given below only if the interfacing chips supports faster MDC clocks.
Selection MDC Clock 1000 pclk_gmac/4
1001 pclk_gmac/6
1010 pclk_gmac/8
1011 pclk_gmac/10
1100 pclk_gmac/12
1101 pclk_gmac/14
1110 pclk_gmac/16
1111 pclk_gmac/18




Bit

Attr

Reset Value

Description

1


RW


0x0


GW
GMII Write
When set, this bit tells the PHY that this will be a Write operation using register GMAC_GMII_DATA. If this bit is not set, this will be a Read operation, placing the data in
register GMAC_GMII_DATA.

0


W1C


0x0


GB
GMII Busy
This bit should read a logic 0 before writing to Register GMII_ADDR and Register GMII_DATA. This bit must also be set to 0 during a Write to Register GMII_ADDR. During a PHY register access, this bit will be set to 1'b1 by the Application to indicate that a Read or Write access is in progress. Register GMII_DATA (GMII Data) should be kept valid until this bit is cleared by the GMAC during a PHY Write operation. The Register GMII_DATA is invalid until this bit is cleared by the GMAC during a PHY Read operation. The Register GMII_ADDR (GMII Address) should not be
written to until this bit is cleared.


Only
GMAC_GMII_DATA



T-chip
Address: Operational Base + offset (0x0014) GMII Data Register

Bit

Attr

Reset Value

Description

31:16

RO

0x0

reserved

15:0


RW


0x0000


GD
GMII Data
This contains the 16-bit data value read from the PHY after a Management Read
operation or the 16-bit data value to be written to the PHY before a Management Write
operation.



GMAC_FLOW_CTRL


Address: Operational Base + offset (0x0018) Flow Control Register

Bit

Attr

Reset Value

Description


Only

T-chip



Bit

Attr

Reset Value

Description

31:16

RW

0x0000

PT
Pause Time
This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, then consecutive writes to this register should be performed only after at least 4 clock cycles in the destination clock
domain.

15:8

RO

0x0

reserved

7


RW


0x0


DZPQ
Disable Zero-Quanta Pause
When set, this bit disables the automatic generation of Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i).
When this bit is reset, normal operation with
automatic Zero-Quanta Pause Control frame generation is enabled.

6

RO

0x0

reserved

5:4

RW

0x0

PLT
Pause Low Threshold
This field configures the threshold of the PAUSE timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of PAUSE Frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 100H (256 slot-times), and PLT = 01, then a second PAUSE frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256-28) slot-times after the first PAUSE frame is transmitted.
Selection Threshold
00 Pause time minus 4 slot times 01 Pause time minus 28 slot times

  1. Pause time minus 144 slot times

  2. Pause time minus 256 slot times Slot time is defined as time taken to transmit 512 bits (64 bytes) on the

GMII/MII interface.


Only

T-chip




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