Chapter 41 gmac ethernet Interface



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Bit

Attr

Reset Value

Description

31:22

RO

0x0

reserved

21


RW


0x0


INT21
The bit is set when the rxfifooverflow counter reaches half the maximum value, and also when it reaches the maximum value.

20:19

RO

0x0

reserved

18


RC


0x0


INT18
The bit is set when the rxlengtherror counter reaches half the maximum value, and also when it reaches the maximum value.

17:6

RO

0x0

reserved

5


RW


0x0


INT5
The bit is set when the rxcrcerror counter reaches half the maximum value, and also when it reaches the maximum value.




Bit

Attr

Reset Value

Description

4


RC


0x0


INT4
The bit is set when the rxmulticastframes_g counter reaches half the maximum value, and also when it reaches the maximum value.

3

RO

0x0

reserved

2


RC


0x0


INT2
The bit is set when the rxoctetcount_g counter reaches half the maximum value, and also when it reaches the maximum value.

1


RC


0x0


INT1
The bit is set when the rxoctetcount_gb counter reaches half the maximum value, and also when it reaches the maximum value.

0


RC


0x0


INT0
The bit is set when the rxframecount_gb counter reaches half the maximum value, and also when it reaches the maximum value.


Only
GMAC_MMC_TX_INTR



T-chip
Address: Operational Base + offset (0x0108) MMC Transmit Interrupt Register

Bit

Attr

Reset Value

Description

31:22

RO

0x0

reserved

21


RC


0x0


INT21
The bit is set when the txframecount_g counter reaches half the maximum value, and also when it reaches the maximum value.

20


RC


0x0


INT20
The bit is set when the txoctetcount_g counter reaches half the maximum value, and also when it reaches the maximum value.

19


RC


0x0


INT19
The bit is set when the txcarriererror counter reaches half the maximum value, and also when it reaches the maximum value.

18:14

RO

0x0

reserved

13


RC


0x0


INT13
The bit is set when the txunderflowerror counter reaches half the maximum value, and also when it reaches the maximum value.

12:2

RO

0x0

reserved

1


RC


0x0


INT1
The bit is set when the txframecount_gb counter reaches half the maximum value, and also when it reaches the maximum value.


Only

T-chip



Bit

Attr

Reset Value

Description

0


RC


0x0


INT0
The bit is set when the txoctetcount_gb counter reaches half the maximum value, and also when it reaches the maximum value.

GMAC_MMC_RX_INT_MSK


Address: Operational Base + offset (0x010c) MMC Receive Interrupt Mask Register

Bit

Attr

Reset Value

Description

31:22

RO

0x0

reserved

21

RW

0x0

INT21
Setting this bit masks the interrupt when the rxfifooverflow counter reaches half the maximum value, and also when it reaches the maximum value.

20:19

RO

0x0

reserved

18

RW

0x0

INT18
Setting this bit masks the interrupt when the rxlengtherror counter reaches half the maximum value, and also when it reaches the maximum value.

17:6

RO

0x0

reserved

5

RW

0x0

INT5
Setting this bit masks the interrupt when the rxcrcerror counter reaches half the maximum value, and also when it reaches the maximum value.

4

RW

0x0

INT4
Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half the maximum value, and also when it reaches the maximum value.

3

RO

0x0

reserved

2

RW

0x0

INT2
Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half the maximum value, and also when it reaches the maximum value.

1

RW

0x0

INT1
Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half the maximum value, and also when it reaches the
maximum value.




Bit

Attr

Reset Value

Description

0

RW

0x0

INT0
Setting this bit masks the interrupt when the rxframecount_gb counter reaches half the maximum value, and also when it reaches the
maximum value.

GMAC_MMC_TX_INT_MSK



Only

T-chip
Address: Operational Base + offset (0x0110) MMC Transmit Interrupt Mask Register

Bit

Attr

Reset Value

Description

31:22

RO

0x0

reserved

21

RW

0x0

INT21
Setting this bit masks the interrupt when the txframecount_g counter reaches half the maximum value, and also when it reaches the maximum value.

20

RW

0x0

INT20
Setting this bit masks the interrupt when the txoctetcount_g counter reaches half the maximum value, and also when it reaches the maximum value.

19

RW

0x0

INT19
Setting this bit masks the interrupt when the txcarriererror counter reaches half the maximum value, and also when it reaches the maximum value.

18:14

RO

0x0

reserved

13

RW

0x0

INT13
Setting this bit masks the interrupt when the txunderflowerror counter reaches half the maximum value, and also when it reaches the maximum value.

12:2

RO

0x0

reserved

1

RW

0x0

INT1
Setting this bit masks the interrupt when the txframecount_gb counter reaches half the maximum value, and also when it reaches the maximum value.

0

RW

0x0

INT0
Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half the maximum value, and also when it reaches the
maximum value.



GMAC_MMC_TXOCTETCNT_GB


Address: Operational Base + offset (0x0114) MMC TX OCTET Good and Bad Counter

Bit

Attr

Reset Value

Description

31:0


RW


0x00000000



txoctetcount_gb
Number of bytes transmitted, exclusive of preamble and retried bytes, in good and bad
frames.



GMAC_MMC_TXFRMCNT_GB


Address: Operational Base + offset (0x0118) MMC TX Frame Good and Bad Counter

Bit

Attr

Reset Value

Description

31:0


RW


0x00000000



txframecount_gb
Number of good and bad frames transmitted, exclusive of retried frames.



GMAC_MMC_TXUNDFLWERR



Only
Address: Operational Base + offset (0x0148) MMC TX Underflow Error

Bit

Attr

Reset Value

Description

31:0


RW


0x00000000



txunderflowerror
Number of frames aborted due to frame underflow error.



GMAC_MMC_TXCARERR



T-chip
Address: Operational Base + offset (0x0160) MMC TX Carrier Error

Bit

Attr

Reset Value

Description

31:0


RW


0x00000000



txcarriererror
Number of frames aborted due to carrier sense error (no carrier or loss of carrier).



GMAC_MMC_TXOCTETCNT_G


Address: Operational Base + offset (0x0164) MMC TX OCTET Good Counter

Bit

Attr

Reset Value

Description

31:0


RW


0x00000000



txoctetcount_g
Number of bytes transmitted, exclusive of preamble, in good frames only.



GMAC_MMC_TXFRMCNT_G


Address: Operational Base + offset (0x0168) MMC TX Frame Good Counter

Bit

Attr

Reset Value

Description

31:0

RW

0x00000000

txframecount_g
Number of good frames transmitted.


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