Ladder Logic (lad) for S7-300 and S7-400 Programming
---( # )--- Midline Output
Yüklə 1,39 Mb. Pdf görüntüsü
|
|
1.7 ---( # )--- Midline Output Symbol ---( # )--- Parameter Data Type Memory Area Description BOOL I, Q, M, *L, D Assigned bit * An L area address can only be used if it is declared TEMP in the variable declaration table of a logic block (FC, FB, OB). Description ---( # )--- (Midline Output) is an intermediate assigning element which saves the RLO bit (power flow status) to a specified . The midline output element saves the logical result of the preceding branch elements. In series with other contacts, ---( # )--- is inserted like a contact. A ---( # )--- element may never be connected to the power rail or directly after a branch connection or at the end of a branch. A negated ---( # )--- can be created by using the ---|NOT|--- (invert power flow) element. Bit Logic Instructions 1.8 ---( R ) Reset Coil Ladder Logic (LAD) for S7-300 and S7-400 Programming Reference Manual, 04/2017, A5E41524738-AA 19 MCR (Master Control Relay) dependency MCR dependency is activated only if a midline output coil is placed inside an active MCR zone. Within an activated MCR zone, if the MCR is on and there is power flow to a midline output coil; the addressed bit is set to the current status of power flow. If the MCR is off, a logic "0" is written to the specified address regardless of power flow status. Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: - - - - - 0 X - 1 Example M 1.1 M 2.2 Q 4.0 I 1.0 I 1.1 M 1.1 has the RLO M 0.0 has the RLO M 2.2 has the RLO of the entire bit logic combination I 1.0 I 1.1 I 2.2 I 1.3 M 0.0 I 1.0 I 1.1 I 2.2 I 1.3 NOT ( ) (#) (#) NOT (#) NOT 1.8 ---( R ) Reset Coil Symbol ---( R ) Parameter Data Type Memory Area Description BOOL I, Q, M, L, D, T, C Reset bit Description ---( R ) (Reset Coil) is executed only if the RLO of the preceding instructions is "1" (power flows to the coil). If power flows to the coil (RLO is "1"), the specified of the element is reset to "0". A RLO of "0" (no power flow to the coil) has no effect and the state of the element's specified address remains unchanged. The may also be a timer (T no.) whose timer value is reset to "0" or a counter (C no.) whose counter value is reset to "0". Bit Logic Instructions 1.8 ---( R ) Reset Coil Ladder Logic (LAD) for S7-300 and S7-400 Programming 20 Reference Manual, 04/2017, A5E41524738-AA MCR (Master Control Relay) dependency MCR dependency is activated only if a reset coil is placed inside an active MCR zone. Within an activated MCR zone, if the MCR is on and there is power flow to a reset coil; the addressed bit is reset to the "0" state. If the MCR is off, the current state of the element's specified address remains unchanged regardless of power flow status. Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: - - - - - 0 X - 0 Example I 0.0 I 0.1 I 0.2 R Q 4.0 T1 I 0.3 C1 I 0.4 R R Network 3 Network 2 Network 1 The signal state of output Q4.0 is reset to "0" if one of the following conditions exists: The signal state is "1" at inputs I0.0 and I0.1 Or the signal state is "0" at input I0.2. If the RLO is "0", the signal state of output Q4.0 remains unchanged. The signal state of timer T1 is only reset if: the signal state is "1" at input I0.3. The signal state of counter C1 is only reset if: the signal state is "1" at input I0.4. If the example rungs are within an activated MCR zone: When MCR is on, Q4.0, T1, and C1 are reset as described above. When MCR is off, Q4.0, T1, and C1 are left unchanged regardless of RLO state (power flow status). Bit Logic Instructions 1.9 ---( S ) Set Coil Ladder Logic (LAD) for S7-300 and S7-400 Programming Reference Manual, 04/2017, A5E41524738-AA 21 1.9 ---( S ) Set Coil Symbol ---( S ) Parameter Data Type Memory Area Description BOOL I, Q, M, L, D Set bit Description ---( S ) (Set Coil) is executed only if the RLO of the preceding instructions is "1" (power flows to the coil). If the RLO is "1" the specified of the element is set to "1". An RLO = 0 has no effect and the current state of the element's specified address remains unchanged. MCR (Master Control Relay) dependency MCR dependency is activated only if a set coil is placed inside an active MCR zone. Within an activated MCR zone, if the MCR is on and there is power flow to a set coil; the addressed bit is set to the "1" state. If the MCR is off, the current state of the element's specified address remains unchanged regardless of power flow status. Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: - - - - - 0 X - 0 Example I 0.0 I 0.1 I 0.2 S Q 4.0 The signal state of output Q4.0 is "1" if one of the following conditions exists: The signal state is "1" at inputs I0.0 and I0.1 Or the signal state is "0" at input I0.2. If the RLO is "0", the signal state of output Q4.0 remains unchanged. Bit Logic Instructions 1.10 RS Reset-Set Flip Flop Ladder Logic (LAD) for S7-300 and S7-400 Programming 22 Reference Manual, 04/2017, A5E41524738-AA If the example rungs are within an activated MCR zone: When MCR is on, Q4.0 is set as described above. When MCR is off, Q4.0 is left unchanged regardless of RLO state (power flow status). 1.10 RS Reset-Set Flip Flop Symbol RS S Q R Parameter Data Type Memory Area Description BOOL I, Q, M, L, D Set or reset bit S BOOL I, Q, M, L, D Enabled reset instruction R BOOL I, Q, M, L, D Enabled reset instruction Q BOOL I, Q, M, L, D Signal state of Description RS (Reset-Set Flip Flop) is reset if the signal state is "1" at the R input, and "0" at the S input. Otherwise, if the signal state is "0" at the R input and "1" at the S input, the flip flop is set. If the RLO is "1" at both inputs, the order is of primary importance. The RS flip flop executes first the reset instruction then the set instruction at the specified , so that this address remains set for the remainder of program scanning. The S (Set) and R (Reset) instructions are executed only when the RLO is "1". RLO "0" has no effect on these instructions and the address specified in the instruction remains unchanged. MCR (Master Control Relay) dependency MCR dependency is activated only if a RS flip flop is placed inside an active MCR zone. Within an activated MCR zone, if the MCR is on, the addressed bit is reset to "0" or set to "1" as described above. If the MCR is off, the current state of the specified address remains unchanged regardless of input states. Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: - - - - - x x x 1 Bit Logic Instructions 1.11 SR Set-Reset Flip Flop Ladder Logic (LAD) for S7-300 and S7-400 Programming Reference Manual, 04/2017, A5E41524738-AA 23 Example RS R Q M 0.0 S I 0.0 I 0.1 Q 4.0 If the signal state is "1" at input I0.0 and "0" at I0.1, memory bit M0.0 is set and output Q4.0 is "0". Otherwise, if the signal state at input I0.0 is "0" and at I0.1 is "1", memory bit M0.0 is reset and output Q4.0 is "1". If both signal states are "0", nothing is changed. If both signal states are "1", the set instruction dominates because of the order; M0.0 is set and Q4.0 is "1". If the example is within an activated MCR zone: When MCR is on, Q4.0 is reset or set as described above. When MCR is off, Q4.0 is left unchanged regardless of input states. 1.11 SR Set-Reset Flip Flop Symbol SR S Q R Parameter Data Type Memory Area Description BOOL I, Q, M, L, D Set or reset bit S BOOL I, Q, M, L, D Enable set instruction R BOOL I, Q, M, L, D Enable reset instruction Q BOOL I, Q, M, L, D Signal state of Description SR (Set-Reset Flip Flop) is set if the signal state is "1" at the S input, and "0" at the R input. Otherwise, if the signal state is "0" at the S input and "1" at the R input, the flip flop is reset. If the RLO is "1" at both inputs, the order is of primary importance. The SR flip flop executes first the set instruction then the reset instruction at the specified , so that this address remains reset for the remainder of program scanning. The S (Set) and R (Reset) instructions are executed only when the RLO is "1". RLO "0" has no effect on these instructions and the address specified in the instruction remains unchanged. MCR (Master Control Relay) dependency MCR dependency is activated only if a SR flip flop is placed inside an active MCR zone. Within an activated MCR zone, if the MCR is on ; the addressed bit is set to "1" or reset to "0" as described Bit Logic Instructions 1.12 ---( N )--- Negative RLO Edge Detection Ladder Logic (LAD) for S7-300 and S7-400 Programming 24 Reference Manual, 04/2017, A5E41524738-AA above. If the MCR is off, the current state of the specified address remains unchanged regardless of input states. Status word BR CC1 CC0 OV OS OR STA RLO /FC writes: - - - - - x x x 1 Example SR S Q M 0.0 R I 0.0 I 0.1 Q 4.0 If the signal state is "1" at input I0.0 and "0" at I0.1, memory bit M0.0 is set and output Q4.0 is "1". Otherwise, if the signal state at input I0.0 is "0" and at I0.1 is "1", memory bit M0.0 is reset and output Q4.0 is "0". If both signal states are "0", nothing is changed. If both signal states are "1", the reset instruction dominates because of the order; M0.0 is reset and Q4.0 is "0". If the example is within an activated MCR zone: When MCR is on, Q4.0 is set or reset as described above. When MCR is off, Q4.0 is left unchanged regardless of input states. 1.12 ---( N )--- Negative RLO Edge Detection Symbol ---( N ) Parameter Data Type Memory Area Description BOOL I, Q, M, L, D Edge memory bit, storing the previous signal state of RLO Description ---( N )--- (Negative RLO Edge Detection) detects a signal change in the address from "1" to "0" and displays it as RLO = "1" after the instruction. The current signal state in the RLO is compared with the signal state of the address, the edge memory bit. If the signal state of the address is "1" and the RLO was "0" before the instruction, the RLO will be "1" (pulse) after this instruction, and "0" in all other cases. The RLO prior to the instruction is stored in the address. Bit Logic Instructions 1.13 ---( P )--- Positive RLO Edge Detection Ladder Logic (LAD) for S7-300 and S7-400 Programming Reference Manual, 04/2017, A5E41524738-AA 25 Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: - - - - - 0 x x 1 Example N M 0.0 I 0.0 I 0.1 I 0.2 JMP CAS1 The edge memory bit M0.0 saves the old RLO state. When there is a signal change at the RLO from "1" to "0", the program jumps to label CAS1. 1.13 ---( P )--- Positive RLO Edge Detection Symbol ---( P )--- Parameter Data Type Memory Area Description BOOL I, Q, M, L, D Edge memory bit, storing the previous signal state of RLO Description ---( P )--- (Positive RLO Edge Detection) detects a signal change in the address from "0" to "1" and displays it as RLO = "1" after the instruction. The current signal state in the RLO is compared with the signal state of the address, the edge memory bit. If the signal state of the address is "0" and the RLO was "1" before the instruction, the RLO will be "1" (pulse) after this instruction, and "0" in all other cases. The RLO prior to the instruction is stored in the address. Status word BR CC1 CC0 OV OS OR STA RLO /FC writes: - - - - - 0 X X 1 Bit Logic Instructions 1.14 ---(SAVE) Save RLO into BR Memory Ladder Logic (LAD) for S7-300 and S7-400 Programming 26 Reference Manual, 04/2017, A5E41524738-AA Example CAS1 P M 0.0 JMP I 0.0 I 0.1 I 0.2 The edge memory bit M0.0 saves the old RLO state. When there is a signal change at the RLO from "0" to "1", the program jumps to label CAS1. 1.14 ---(SAVE) Save RLO into BR Memory Symbol ---( SAVE ) Description ---(SAVE) (Save RLO into BR Memory) saves the RLO to the BR bit of the status word. The first check bit /FC is not reset. For this reason, the status of the BR bit is included in the AND logic operation in the next network. For the instruction "SAVE" (LAD, FBD, STL), the following applies and not the recommended use specified in the manual and online help: We do not recommend that you use SAVE and then check the BR bit in the same block or in subordinate blocks, because the BR bit can be modified by many instructions occurring inbetween. It is advisable to use the SAVE instruction before exiting a block, since the ENO output (= BR bit) is then set to the value of the RLO bit and you can then check for errors in the block. Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: X - - - - - - - - Example SAVE I 0.0 I 0.1 I 0.2 Bit Logic Instructions 1.15 NEG Address Negative Edge Detection Ladder Logic (LAD) for S7-300 and S7-400 Programming Reference Manual, 04/2017, A5E41524738-AA 27 The status of the rung (=RLO) is saved to the BR bit. 1.15 NEG Address Negative Edge Detection Symbol NEG M_BIT Q Parameter Data Type Memory Area Description BOOL I, Q, M, L, D Scanned signal BOOL I, Q, M, L, D M_BIT edge memory bit, storing the previous signal state of Q BOOL I, Q, M, L, D One shot output Description NEG (Address Negative Edge Detection) compares the signal state of state from the previous scan, which is stored in previous state was "1" (detection of negative edge), the RLO bit will be "1" after this instruction. Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: - - - - - x 1 x 1 Example NEG M_BIT Q I 0.3 M 0.0 I 0.0 ( ) I 0.1 I 0.2 I 0.4 Q 4.0 The signal state at output Q4.0 is "1" if the following conditions exist: • The signal state is "1" at inputs I0.0 and I0.1 and I0.2 • And there is a negative edge at input I0.3 • And the signal state is "1" at input I0.4 Bit Logic Instructions 1.16 POS Address Positive Edge Detection Ladder Logic (LAD) for S7-300 and S7-400 Programming 28 Reference Manual, 04/2017, A5E41524738-AA 1.16 POS Address Positive Edge Detection Symbol POS M_BIT Q Parameter Data Type Memory Area Description BOOL I, Q, M, L, D Scanned signal BOOL I, Q, M, L, D M_BIT edge memory bit, storing the previous signal state of Q BOOL I, Q, M, L, D One shot output Description POS (Address Positive Edge Detection) compares the signal state of state from the previous scan, which is stored in previous state was "0" (detection of rising edge), the RLO bit will be "1" after this instruction. Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: - - - - - x 1 x 1 Example POS M_BIT Q I 0.3 M 0.0 I 0.0 ( ) I 0.1 I 0.2 I 0.4 Q 4.0 The signal state at output Q4.0 is "1" if the following conditions exist: • The signal state is "1" at inputs I0.0 and I0.1 and I0.2 • And there is a positive edge at input I0.3 • And the signal state is "1" at input I0.4 Bit Logic Instructions 1.17 Immediate Read Ladder Logic (LAD) for S7-300 and S7-400 Programming Reference Manual, 04/2017, A5E41524738-AA 29 1.17 Immediate Read Description For the Immediate Read function, a network of symbols must be created as shown in the example below. For time-critical applications, the current state of a digital input may be read faster than the normal case of once per OB1 scan cycle. An Immediate Read gets the state of a digital input from an input module at the time the Immediate Read rung is scanned. Otherwise, you must wait for the end of the next OB1 scan cycle when the I memory area is updated with the P memory state. To perform an immediate read of an input (or inputs) from an input module, use the peripheral input (PI) memory area instead of the input (I) memory area. The peripheral input memory area can be read as a byte, a word, or a double word. Therefore, a single digital input cannot be read via a contact (bit) element. To conditionally pass voltage depending on the status of an immediate input: 1. A word of PI memory that contains the input data of concern is read by the CPU. 2. The word of PI memory is then ANDed with a constant that yields a non-zero result if the input bit is on ("1"). 3. The accumulator is tested for non-zero condition. Example Ladder Network with Immediate Read of Peripheral Input I1.1 WAND_W EN OUT IN2 ENO IN1 16#0002 PIW1 MWx * I 4.1 <>0 I 4.5 * MWx has to be specified in order to be able to store the network. x may be any permitted number. Description of WAND_W instruction: PIW1 0000000000101010 W#16#0002 0000000000000010 Result 0000000000000010 In this example immediate input I1.1 is in series with I4.1 and I4.5. The word PIW1 contains the immediate status of I1.1. PIW1 is ANDed with W#16#0002. The result is not equal to zero if I1.1 (second bit) in PB1 is true ("1"). The contact A<>0 passes voltage if the result of the WAND_W instruction is not equal to zero. Bit Logic Instructions 1.18 Immediate Write Ladder Logic (LAD) for S7-300 and S7-400 Programming 30 Reference Manual, 04/2017, A5E41524738-AA Yüklə 1,39 Mb. Dostları ilə paylaş:
|