The PIC16F84 has 13 I/O lines, divided up into two ports. Port A has five I/O lines mapped into the Data store address space at File 5. The remaining eight lines are allocated to PortB at File 6. These ports can be thought of as a ‘window’ into the Data store in that data written to File 5 or File 6 appear to the outside world on the corresponding pins; pins RA4…RA0 and RB7…RB0 respectively. However, the electrical and logic behavior of these ports is more complex than that of a purely internal register file. This will be discussed in topic 11 but as an example a port bit must be configurable as either an output (so that the CPU can control the state of the associated pin) or an input (so that the CPU can read the state of this pin). To do this, each Port register has an associated Data Direction register, which Microchip call TRISA and TRISB, which map to File 85h and File 86h respectively (the term TRIS stands for TRIState.These registers lie in the less convenient Bank 1 as they are usually set up at the beginning of the program and never subsequently altered.
As an example, consider that we wish to make Port B bits 6.0 an input and bit 7 an output. Then the setting up code would be:
As an example, subsequently pin RB7 can be pulsed high and then low as follows:
with the assumption that the CPU is still in Bank0. The registers associated with parallel I/O are:
PORTA, File05h Only the lower five bits are implemented in this register file, feeding through to pins RA4.RA0. Pin RA4 is shared with the Timer peripheral. The upper three bits read as zero.
TRISA, File 85h This is used to bitwise configure Port A bits as input or output. Setting TRISA[n] to 1 sets bit PORTA[n] as an input and to 0 as an output. Any type of reset sets the TRIS bits to 1 and the associated port bits to input.
PORTB, File06h A bi-directional 8-bit port connected to pins RB7…RB0. Bit RB0 doubles as a hardware interrupt input.
TRISB, File 86h This is used to bitwise configure Port B bits as input or output. Details are the same as TRISA.
