The execution circuitry is centered around the Arithmetic Logic Unit (ALU) – see Fig. 2.19.The ALU processes data from up to two sources. One of these is the 8-bit Working register. The other can be multiplexed either from a file in the Data store or an 8-bit literal, which is part of the instruction code. For example addwf 20h,w and addlw 5 respectively add the contents of W to that of File 20h or the constant 5 to W. The outcome can be switched back into W (eg. addwf 20h,w) or into the register file (eg. addwf 20h,f) as controlled by the single Destination bit in the instruction code.
Where an operand is a file, the execution unit can generate the Data store address in one of two ways – see Fig. 4.6.
• Directly via a 7-bit address field in the instruction.Seven bits can only directly address up to 128 files. This can be increased to 256 files if the state of the RP0 bit in the Status register (see Fig. 4.5) is also multiplexed in as part of the Data store address.
• Indirectly using the File Select Register in conjunction with Indirect addressing, as described in Fig. 3.6. In this situation the 8-bit address in the FSR is used to address the Data store whenever the virtual location File 0 is addressed. Here potentially all 256 files in both banks can be addressed irrespective of the state of RP0.
The three flag bits in the Status register STATUS are associated with the ALU, giving status information concerning the outcome from an instruction.
Carry flag
Bit 0 of the Status register is the C flag. This primarily holds the Carry out from the last addition operation. Subtraction operations activate this bit as the complement of the Borrow out. For example, 24 – 12 = 12E1 and 12 – 24 = 88B0. C also functions as an input/output bit for the Rotate instructions, as shown in Fig. 3.7.
The label R/W ? in Fig. 4.5 indicates that this bit can be read from or written to and has an indeterminate value on a power-up reset – its value does not alter on any other type of reset.