Execute The execution circuitry is centered

The Data store comprises 81 8-bit locations known as file registers or just files for short. The contents of any location in the Data store may be moved into or out of the Working register. The PIC16F84′s file registers are located in the Data store’s memory map as shown in Fig. 4.6. The registers can be categorised as Special-Purpose Registers (SPRs) used by the core CPU and peripheral modules for status information and controlling the desired operation of the device. The remaining implemented General-Purpose Registers (GPR) can be used by the programmer for temporary storage of program variables.
There are two ways an instruction can target a datum in the Data store. Each file register has an address, which is listed in Fig. 4.6. For example PORTA is located at File 05.

Directly

Any instruction which can process a datum in the Data store can directly specify the effective address using seven binary bits which are part of the binary program code. By itself this can address a base range of 00-7Fh. However, we see from Fig. 4.6 that this address is augmented by the RP0 bit19 in the Status register to give an effective 8-bit address. If RP0 is 0 (as it is after reset) the range is 00-7Fh, that is Bank0. If RP0 is made 1 then the range is 80-FFh; that is Bank1. For example, to set the contents of File register TRISB (File 86h) to all 1 s and then to read the contents of the File register PORTB into the Working register, we need the following program:

Fig. 4.6 Data store memory map.

Indirectly

If the Indirect address mode is used, as was described in Fig. 3.6, then the 8-bit address in the File Select Register (FSR) is used as the effective. As we have an 8-bit address in this situation any location in the two banks are accessible with not bank switching required. The same example as described above is then implemented as:

Although there is no Bank switching required, this code segment is actually longer than the previous solution! However, Indirect addressing is useful when one location in Bank 1 requires frequent access.
The bottom 12 locations of both banks are reserved for SPRs. Although the exact location can vary across members of the mid-range family, common registers; for example, PCL and PORTA tend to have the same location.
Of these, we have already met most of those involved with the core function: INDF
The INDirect File at File 0 is not physically implemented as a register. Instructions accessing this virtual location actually put the contents of the FSR onto the Data store address bus, as described in Fig. 3.6.
PCL
The Program Counter Low byte is addressed as File 2. Its relationship with the total 13-bit PC is described on Fig. 4.3.
STATUS
The Status register can be accessed in File 3. As can be seen from Fig. 4.5, this file holds the three code condition bits plus several status bits and the Data store page bit RP0.
FSR
The File Select Register at File 4 holds the indirect address used when the instruction refers to the virtual INDF address.
PCLATH
File 0Ah holds the LATch High byte for the Program Counter, as described in Fig. 4.3.
INTCON
The INTerrupt CONtrol register at File 0Bh holds the mask and status bits controlling the response of the MCU to interrupts. Its operation is described in topic 7.
All these core SPRs are images in both memory banks.
The remaining nine SPRs relate to the configuration and control of the various peripheral interface devices. More details will be given on individual peripheral SPRs in Part 3 of the topic in the appropriate topics.
The 68 GPRs are located from File 0Ch through File4Fh and are mirrored in Bank 1.20 Thus the instruction clrf 4Fh and clrf 0Cfh are identical and target the same physical location irrespective of the state of the Register Page bit RP0 setting. The remaining file locations are not implemented and read as 00h, as does location File 07h/File 87h – which is reserved for PORTC and TRISC in devices with 28+ pins.

Peripheral functions

Each member of the PIC family has its unique set of integrated peripheral devices. However, all PICs have parallel input/output and timer facilities. As well as these standard facilities, the PIC16F84 has a peripheral 64-byte EEPROM which can be used as a small data store not dependent on continuous power to retain its contents; i.e. non-volatile.
Each of these peripheral facilities are described in detail in Part 3 of the topic, but for completeness are briefly cataloged here together with their associated SPRs. These registers are used to configure the function of their target peripheral interface, to control and monitor their status.

Parallel input/output

The ability to externally alter or monitor several digital lines at the same time is a virtually universal facility on microprocessor-based systems.
Apart from the 8-pin PIC12XXX series, all PICs have a minimum of 12 such external input/output lines. Some have much more, such as the 40-pin PIC16C74 which has 33 I/O lines.