In this topic we introduce the pic16F84 mcu

There is one problem with this example, which arises because the PC is actually 13-bits wide and File 2 only holds the lower eight bits, PC[7...0]. The upper five bits, PC[12...8] are held in a ‘buried’ register; that is not directly accessible to the programmer. Actually any instruction that directly writes to File 2, such as our example above, does change all 13 PC bits as shown in Fig. 4.3. Not only will the 8-bit outcome of the instruction addwf 2,f be placed in the lower byte of the PC but the lower five bits of the PC buffer register at File 0Ah, labelled PCLATH (for Program Counter LATch High byte) in Fig. 4.3, are automatically copied into the high byte of the Program Counter. The PCLATH file data register is cleared when the PIC is reset and so an instruction like our example will usually result in an address in the first 256-byte.Thus care needs to be taken when altering the state of the PC by writing to PCL in this manner; especially if the outcome overflows its 8-bit field. Instructions that indirectly alter the value of the PC, such as goto, will also use part of the contents of PCLATH in updating the PC. Such instructions carry an 11-bit address as part of the instruction code. Here bits PCLATH[4:3] are moved over to the corresponding PC bits 12 & 11 to give a complete 13-bit PC update.
Associated with the Program Counter is an area of buried storage that can stack up to eight copies of the PC. The current value of the PC is pushed into this stack when a subroutine is called or an interrupt is serviced. Conversely a return from a subroutine or interrupt causes the last stacked PC value to be popped out again into the PC. Details are given in topics 6 and 7.

Fig. 4.3 Showing how all 13 bits of the Program Counter are altered when writing to PCL.
The PIC microcontrollers have an integral oscillator that generates the internal timing sequences. The oscillator frequency fosc is normally controlled by an external crystal (or ceramic)-capacitor network across the device OSC1 and OSC2 pins.A resistor-capacitor connected to OSC1 may be used as the timing elements where lower precision and frequency stability is not an issue. In this case OSC2/CLKOUT outputs a signal of frequency 4 x fosc. Alternatively an external oscillator can be used as the master clock into OSC1/CLKIN. The PIC16F84 has a maximum frequency fOsc of 10 MHz but there is no minimum. As we shall see (Fig. 10.2 )the lower the frequency the smaller is the power consumption. Unless otherwise stated, we will assume a fosc of 4 MHz for the rest of the text.
The internal oscillator/clock circuitry must be configured to the appropriate mode, as described in Fig. 10.5. This is normally done when code is blasted into the Program store flash EEPROM. When the PIC is powered up (external supply voltage is applied) a 72 ms internal reset pulse is generated by the Power-up timer after the supply rises above approximately 2 volts, followed by 1024 clock pulses, counted by the Oscillator Start-Up timer to ensure that the internal oscillator has stabilised. This latter guard timer only operates for crystal-type oscillator modes. The Power-Up timer does not operate if an external reset is applied to the Master CLeaR (MCLR) pin.

Fig. 4.4 Internal clock sequencing waveforms.
The clock input/crystal frequency at the OSC1 pin is divided by four to generate four internal non-overlapping quadrature clocks, as shown in Fig. 4.4. The clock-related sequence of operations in the fetch unit are: Q1: Increment the Program Counter and copy onto the Program store address bus.
Q4: Read the instruction code off the Program store data bus into Instruction register 1 and at the same time move the previous instruction down the pipeline into Instruction register 2, where it is presented to the Instruction decoder.