Chapter 41 gmac ethernet Interface



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Bit

Attr

Reset Value

Description

31:4

RO

0x0

reserved

3

RW

0x0

PIM
PMT Interrupt Mask
This bit when set, will disable the assertion of the interrupt signal due to the setting of PMT Interrupt Status bit in Register GMAC_INT_STATUS.

2:1

RO

0x0

reserved

0

RW

0x0

RIM
RGMII Interrupt Mask
This bit when set, will disable the assertion of the interrupt signal due to the setting of RGMII Interrupt Status bit in Register GMAC_INT_STATUS.



GMAC_MAC_ADDR0_HI


Address: Operational Base + offset (0x0040) MAC Address0 High Register

Bit

Attr

Reset Value

Description




Bit

Attr

Reset Value

Description

31:16

RO

0x0

reserved

15:0


RW


0xffff


A47_A32
MAC Address0 [47:32]
This field contains the upper 16 bits (47:32) of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit
Flow Control (PAUSE) Frames.

GMAC_MAC_ADDR0_LO


Address: Operational Base + offset (0x0044) MAC Address0 Low Register

Bit

Attr

Reset Value

Description

31:0


RW


0xffffffff



A31_A0
MAC Address0 [31:0]
This field contains the lower 32 bits of the
6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames.




Only
GMAC_AN_CTRL



T-chip
Address: Operational Base + offset (0x00c0) AN Control Register

Bit

Attr

Reset Value

Description

31:13

RO

0x0

reserved

12

RW

0x0

ANE
Auto-Negotiation Enable
When set, will enable the GMAC to perform auto-negotiation with the link partner.
Clearing this bit will disable auto-negotiation.

11:10

RO

0x0

reserved

9

R/WSC

0x0

RAN
Restart Auto-Negotiation
When set, will cause auto-negotiation to restart if the ANE is set. This bit is self-clearing after auto-negotiation starts. This bit should be cleared for normal operation.

8:0

RO

0x0

reserved



GMAC_AN_STATUS


Address: Operational Base + offset (0x00c4) AN Status Register

Bit

Attr

Reset Value

Description

31:6

RO

0x0

reserved




Bit

Attr

Reset Value

Description

5

RO

0x0

ANC
Auto-Negotiation Complete
When set, this bit indicates that the auto-negotiation process is completed.
This bit is cleared when auto-negotiation is
reinitiated.

4

RO

0x0

reserved

3


RO


0x1


ANA
Auto-Negotiation Ability
This bit is always high, because the GMAC supports auto-negotiation.

2

R/WSC

0x0

LS
Link Status
When set, this bit indicates that the link is up. When cleared, this bit indicates that the link is down.

1:0

RO

0x0

reserved


Only
GMAC_AN_ADV



T-chip
Address: Operational Base + offset (0x00c8) Auto_Negotiation Advertisement Register

Bit

Attr

Reset Value

Description

31:16

RO

0x0

reserved

15


RO


0x0


NP
Next Page Support
This bit is tied to low, because the GMAC does not support the next page.

14

RO

0x0

reserved

13:12

RW

0x0

RFE
Remote Fault Encoding
These 2 bits provide a remote fault encoding, indicating to a link partner that a fault or error condition has occurred.

11:9

RO

0x0

reserved

8:7

RW

0x3

PSE
Pause Encoding
These 2 bits provide an encoding for the PAUSE bits, indicating that the GMAC is capable of configuring the PAUSE function as defined in IEEE 802.3x.


T-chip



Bit

Attr

Reset Value

Description

6

RW

0x1

HD
Half-Duplex
This bit, when set high, indicates that the GMAC supports Half-Duplex. This bit is tied to low (and RO) when the GMAC is configured for
Full-Duplex-only operation.

5


RW


0x1


FD
Full-Duplex
This bit, when set high, indicates that the GMAC supports Full-Duplex.

4:0

RO

0x0

reserved

GMAC_AN_LINK_PART_AB



Only
Address: Operational Base + offset (0x00cc) Auto_Negotiation Link Partner Ability Register

Bit

Attr

Reset Value

Description

31:16

RO

0x0

reserved

15

RO

0x0

NP
Next Page Support
When set, this bit indicates that more next page information is available.
When cleared, this bit indicates that next page
exchange is not desired.

14


RO


0x0


ACK
Acknowledge
When set, this bit is used by the
auto-negotiation function to indicate that the link partner has successfully received the GMAC's base page. When cleared, it indicates that a successful receipt of the base page has not been achieved.

13:12

RO

0x0

RFE
Remote Fault Encoding
These 2 bits provide a remote fault encoding, indicating a fault or error condition of the link partner.

11:9

RO

0x0

reserved

8:7

RO

0x0

PSE
Pause Encoding
These 2 bits provide an encoding for the PAUSE bits, indicating that the link partner's capability of configuring the PAUSE function
as defined in IEEE 802.3x.




Bit

Attr

Reset Value

Description

6


RO


0x0


HD
Half-Duplex
When set, this bit indicates that the link partner has the ability to operate in
Half-Duplex mode. When cleared, the link
partner does not have the ability to operate in Half-Duplex mode.

5


RO


0x0


FD
Full-Duplex
When set, this bit indicates that the link partner has the ability to operate in
Full-Duplex mode. When cleared, the link partner does not have the ability to operate in
Full-Duplex mode.

4:0

RO

0x0

reserved

GMAC_AN_EXP



Only

T-chip
Address: Operational Base + offset (0x00d0) Auto_Negotiation Expansion Register

Bit

Attr

Reset Value

Description

31:3

RO

0x0

reserved

2


RO


0x0


NPA
Next Page Ability
This bit is tied to low, because the GMAC does not support next page function.

1

RO

0x0

NPR
New Page Received
When set, this bit indicates that a new page has been received by the GMAC. This bit will be cleared when read.

0

RO

0x0

reserved



GMAC_INTF_MODE_STA


Address: Operational Base + offset (0x00d8) RGMII Status Register

Bit

Attr

Reset Value

Description

31:4

RO

0x0

reserved

3


RO


0x0


LST
Link Status
Indicates whether the link is up (1'b1) or down (1'b0)


T-chip



Bit

Attr

Reset Value

Description

2:1

RO

0x0

LSD
Link Speed
Indicates the current speed of the link: 2'b00: 2.5 MHz
2'b01: 25 MHz
2'b10: 125 MHz

0

RW

0x0

LM
Link Mode
Indicates the current mode of operation of the link:
1'b0: Half-Duplex mode
1'b1: Full-Duplex mode

GMAC_MMC_CTRL



Only
Address: Operational Base + offset (0x0100) MMC Control Register


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