Chapter 41 gmac ethernet Interface



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GMAC_MMC_RXFRMCNT_GB


Address: Operational Base + offset (0x0180) MMC RX Frame Good and Bad Counter

Bit

Attr

Reset Value

Description

31:0

RW

0x00000000

rxframecount_gb
Number of good and bad frames received.



GMAC_MMC_RXOCTETCNT_GB


Address: Operational Base + offset (0x0184) MMC RX OCTET Good and Bad Counter

Bit

Attr

Reset Value

Description

31:0


RW


0x00000000



rxoctetcount_gb
Number of bytes received, exclusive of preamble, in good and bad frames.



GMAC_MMC_RXOCTETCNT_G



Only
Address: Operational Base + offset (0x0188) MMC RX OCTET Good Counter

Bit

Attr

Reset Value

Description

31:0


RW


0x00000000



rxoctetcount_g
Number of bytes received, exclusive of preamble, only in good frames.



GMAC_MMC_RXMCFRMCNT_G



T-chip
Address: Operational Base + offset (0x0190) MMC RX Mulitcast Frame Good Counter

Bit

Attr

Reset Value

Description

31:0

RW

0x00000000

rxmulticastframes_g
Number of good multicast frames received.



GMAC_MMC_RXCRCERR


Address: Operational Base + offset (0x0194) MMC RX Carrier

Bit

Attr

Reset Value

Description

31:0

RW

0x00000000

rxcrcerror
Number of frames received with CRC error.



GMAC_MMC_RXLENERR


Address: Operational Base + offset (0x01c8) MMC RX Length Error

Bit

Attr

Reset Value

Description

31:0


RW


0x00000000



rxlengtherror
Number of frames received with length error (Length type field ≠frame size), for all frames with valid length field.


Only

T-chip


GMAC_MMC_RXFIFOOVRFLW


Address: Operational Base + offset (0x01d4) MMC RX FIFO Overflow

Bit

Attr

Reset Value

Description

31:0


RW


0x00000000



rxfifooverflow
Number of missed received frames due to FIFO overflow.



GMAC_MMC_IPC_INT_MSK


Address: Operational Base + offset (0x0200)
MMC Receive Checksum Offload Interrupt Mask Register

Bit

Attr

Reset Value

Description

31:30

RO

0x0

reserved

29

RW

0x0

INT29
Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half the maximum value, and also when it reaches the maximum value.

28

RO

0x0

reserved

27

RW

0x0

INT27
Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half the maximum value, and also when it reaches the
maximum value.

26

RO

0x0

reserved

25

RW

0x0

INT25
Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half the maximum value, and also when it reaches the maximum value.

24:23

RO

0x0

reserved

22

RW

0x0

INT22
Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half the maximum value, and also when it reaches the maximum value.

21:18

RO

0x0

reserved

17

RW

0x0

INT17
Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half the maximum value, and also when it reaches the
maximum value.

16:14

RO

0x0

reserved


Only



Bit

Attr

Reset Value

Description

13

RW

0x0

INT13
Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half the maximum value, and also when it reaches the
maximum value.

12

RO

0x0

reserved

11

RW

0x0

INT11
Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half the maximum value, and also when it reaches the maximum value.

10

RO

0x0

reserved

9

RW

0x0

INT9
Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half the maximum value, and also when it reaches the maximum value.

8:7

RO

0x0

reserved

6

RW

0x0

INT6
Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half the maximum value, and also when it reaches the
maximum value.

5

RW

0x0

INT5
Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half the maximum value, and also when it reaches the maximum value.

4:2

RO

0x0

reserved

1

RW

0x0

INT1
Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half the maximum value, and also when it reaches the maximum value.

0

RW

0x0

INT0
Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half the maximum value, and also when it reaches the maximum value.


T-chip
GMAC_MMC_IPC_INTR


Address: Operational Base + offset (0x0208) MMC Receive Checksum Offload Interrupt Register

Bit

Attr

Reset Value

Description

31:30

RO

0x0

reserved


Only

T-chip



Bit

Attr

Reset Value

Description

29


RC


0x0


INT29
The bit is set when the rxicmp_err_octets counter reaches half the maximum value, and also when it reaches the maximum value.

28

RO

0x0

reserved

27


RC


0x0


INT27
The bit is set when the rxtcp_err_octets counter reaches half the maximum value, and also when it reaches the maximum value.

26

RO

0x0

reserved

25


RC


0x0


INT25
The bit is set when the rxudp_err_octets counter reaches half the maximum value, and also when it reaches the maximum value.

24:23

RO

0x0

reserved

22


RC


0x0


INT22
The bit is set when the rxipv6_hdrerr_octets counter reaches half the maximum value, and also when it reaches the maximum value.

21:18

RO

0x0

reserved

17


RC


0x0


INT17
The bit is set when the rxipv4_hdrerr_octets
counter reaches half the maximum value, and also when it reaches the maximum value.

16:14

RO

0x0

reserved

13


RC


0x0


INT13
The bit is set when the rxicmp_err_frms counter reaches half the maximum value, and also when it reaches the maximum value.

12

RO

0x0

reserved

11


RC


0x0


INT11
The bit is set when the rxtcp_err_frms counter reaches half the maximum value, and also when it reaches the maximum value.

10

RO

0x0

reserved

9


RC


0x0


INT9
The bit is set when the rxudp_err_frms counter reaches half the maximum value, and also when it reaches the maximum value.

8:7

RO

0x0

reserved

6


RC


0x0


INT6
The bit is set when the rxipv6_hdrerr_frms counter reaches half the maximum value, and also when it reaches the maximum value.





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