Chapter 41 gmac ethernet Interface



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Bit

Attr

Reset Value

Description

4:3

RW

0x0

RTC
Receive Threshold Control
These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are transferred automatically. Note that value of 11 is not applicable if the configured Receive FIFO size is 128 bytes.
These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1.
2'b00: 64
2'b01: 32
2'b10: 96
2'b11: 128

2

RW

0x0

OSF
Operate on Second Frame
When this bit is set, this bit instructs the DMA to process a second frame of Transmit data even before status for first frame is obtained.


Only



Bit

Attr

Reset Value

Description

1

RW

0x0


SR
Start/Stop Receive
When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes incoming frames. Descriptor acquisition is attempted from the current position in the list, which is the address set by register GMAC_RX_DESC_LIST_ADDR or the position retained when the Receive process was previously stopped. If no descriptor is owned by the DMA, reception is suspended and Receive Buffer Unavailable (Register GMAC_STATUS[7]) is set. The Start Receive command is effective only when reception has stopped. If the command was issued before setting register GMAC_RX_DESC_LIST_ADDR, DMA behavior is unpredictable.
When this bit is cleared, RxDMA operation is stopped after the transfer of the current frame. The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the
Suspended state.

0

RO

0x0

reserved


T-chip
GMAC_INT_ENA


Address: Operational Base + offset (0x101c) Interrupt Enable Register


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