Chapter 41 gmac ethernet Interface



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Bit

Attr

Reset Value

Description

4

RW

0x0

OVE
Overflow Interrupt Enable
When this bit is set with Abnormal Interrupt Summary Enable (BIT 15), Receive Overflow Interrupt is enabled. When this bit is reset,
Overflow Interrupt is disabled

3


RW


0x0


TJE
Transmit Jabber Timeout Enable
When this bit is set with Abnormal Interrupt Summary Enable (BIT 15), Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, Transmit Jabber Timeout Interrupt is disabled.

2


RW


0x0


TUE
Transmit Buffer Unavailable Enable
When this bit is set with Normal Interrupt Summary Enable (BIT 16), Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, Transmit Buffer Unavailable Interrupt is disabled.

1


RW


0x0


TSE
Transmit Stopped Enable
When this bit is set with Abnormal Interrupt Summary Enable (BIT 15), Transmission Stopped Interrupt is enabled. When this bit is reset, Transmission Stopped Interrupt is disabled.

0

RW

0x0

TIE
Transmit Interrupt Enable
When this bit is set with Normal Interrupt Summary Enable (BIT 16), Transmit Interrupt is enabled. When this bit is reset, Transmit Interrupt is disabled.


T-chip
GMAC_OVERFLOW_CNT


Address: Operational Base + offset (0x1020) Missed Frame and Buffer Overflow Counter Register


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