Frame_miss_number
Indicates the number of frames missed by the application
This counter is incremented each time the MTL asserts the sideband signal mtl_rxoverflow_o. The counter is cleared when this register is
read with mci_be_i[2] at 1'b1.
Frame_miss_number_2
Indicates the number of frames missed by the controller due to the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame.
The counter is cleared when this register is
read with mci_be_i[0] at 1'b1.
RIWT
RI Watchdog Timer count
Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the RxDMA completes the transfer of a frame for which the RI status bit is not set due to the setting in the corresponding descriptor RDES1[31]. When
the watch-dog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when RI bit is set high due to automatic setting of RI as per RDES1[31] of
any received frame.
GMAC_AXI_BUS_MODE
Address: Operational Base + offset (0x1028) AXI Bus Mode Register
Bit
Attr
ResetValue
Description
Only
T-chip
Bit
Attr
ResetValue
Description
31
RW
0x0
EN_LPI
Enable LPI (Low Power Interface)
When set to 1, enable the LPI (Low Power Interface) supported by the GMAC and accepts the LPI request from the AXI System Clock controller.
When set to 0, disables the Low Power Mode and always denies the LPI request
from the AXI System Clock controller.
30
RW
0x0
UNLCK_ON_MGK_RWK
Unlock on Magic Packet or Remote Wake Up When set to 1, enables it to request coming out of Low Power mode only when Magic Packet or Remote Wake Up Packet is received. When set to 0, enables it requests to come out of Low Power mode when any frame is received.
29:22
RO
0x0
reserved
21:20
RW
0x1
WR_OSR_LMT
AXI Maximum Write Out Standing Request Limit
This value limits the maximum outstanding request on the AXI write interface.
Maximum outstanding requests =
WR_OSR_LMT+1
19:18
RO
0x0
reserved
17:16
RW
0x1
RD_OSR_LMT
AXI Maximum Read Out Standing Request Limit
This value limits the maximum outstanding request on the AXI read interface.
Maximum outstanding requests =
RD_OSR_LMT+1
15:13
RO
0x0
reserved
12
RO
0x0
AXI_AAL
Address-Aligned Beats
This bit is read-only bit and reflects the AAL bit Register0 (register GMAC_BUS_MODE[25]).
When this bit set to 1, it performs
address-aligned burst transfers on both read and write channels.
11:4
RO
0x0
reserved
Bit
Attr
ResetValue
Description
3
RW
0x0
BLEN16
AXI Burst Length 16
When this bit is set to 1, or when UNDEF is set to 1, it is allowed to select a burst length of 16.
2
RW
0x0
BLEN8
AXI Burst Length 8
When this bit is set to 1, or when UNDEF is set to 1, it is allowed to select a burst length of 8.
1
RW
0x0
BLEN4
AXI Burst Length 4
When this bit is set to 1, or when UNDEF is set to 1, it is allowed to select a burst length of 4.
0
RO
0x1
UNDEF
AXI Undefined Burst Length
This bit is read-only bit and indicates the complement (invert) value of FB bit in register GMAC_BUS_MODE[16].
When this bit is set to 1, it is allowed to perform any burst length equal to or below the maximum allowed burst length as programmed in bits[7:1];
When this bit is set to 0, the it is allowed to perform only fixed burst lengths as indicated by BLEN256/128/64/32/16/8/4, or a burst
length of 1.