The DMA in GMAC can communicate with Host driver through descriptor lists and data buffers. The DMA transfers data frames received by the core to the Receive Buffer in the Host memory, and Transmit data frames from the Transmit Buffer in the Host memory. Descriptors that reside in the Host memory act as pointers to these buffers.
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There are two descriptor lists; one for reception, and one for transmission. The base address of each list is written into DMA Registers RX_DESC_LIST_ADDR and TX_DESC_LIST_ADDR, respectively. A descriptor list is forward linked (either implicitly or explicitly). The last descriptor may point back to the first entry to create a ring structure. Explicit chaining of descriptors is accomplished by setting the second address chained in both Receive and Transmit descriptors (RDES1[24] and TDES1[24]). The descriptor lists resides in the Host physical memory address space. Each descriptor can point to a maximum of two buffers. This enables two buffers to be used, physically addressed, rather than contiguous buffers in memory.
A data buffer resides in the Host physical memory space, and consists of an entire frame or part of a frame, but cannot exceed a single frame. Buffers contain only data, buffer status is maintained in the descriptor. Data chaining refers to frames that span multiple data buffers. However, a single descriptor cannot span multiple frames. The DMA will skip to the next frame buffer when end-of-frame is detected. Data chaining can be enabled or disabled
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The descriptor ring and chain structure is shown in following figure.
Fig. 41-10 Descriptor Ring and Chain Structure
Each descriptor contains two buffers, two byte-count buffers, and two address pointers, which enable the adapter port to be compatible with various types of memory management schemes. The descriptor addresses must be aligned to the bus width used (Word/Dword/Lword for 32/64/128-bit buses).
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Fig. 41-11 Rx/Tx Descriptors definition
Receive Descriptor
The GMAC Subsystem requires at least two descriptors when receiving a frame. The Receive state machine of the DMA always attempts to acquire an extra descriptor in anticipation of an incoming frame. (The size of the incoming frame is unknown). Before the RxDMA closes a descriptor, it will attempt to acquire the next descriptor even if no frames are received.
In a single descriptor (receive) system, the subsystem will generate a descriptor error if the receive buffer is unable to accommodate the incoming frame and the next descriptor is not owned by the DMA. Thus, the Host is forced to increase either its descriptor pool or the buffer size. Otherwise, the subsystem starts dropping all incoming frames.
Receive Descriptor 0 (RDES0)
RDES0 contains the received frame status, the frame length, and the descriptor ownership information.
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Table 41-3 Receive Descriptor 0
Bit
Description
31
OWN: Own Bit
When set, this bit indicates that the descriptor is owned by the DMA of the GMAC Subsystem. When this bit is reset, this bit indicates that the descriptor is owned by the Host. The DMA clears this bit either when it completes the frame reception or
when the buffers that are associated with this descriptor are full.
30
AFM: Destination Address Filter Fail
When set, this bit indicates a frame that failed in the DA Filter in the GMAC Core.
29:16
FL: Frame Length
These bits indicate the byte length of the received frame that was transferred to host memory (including CRC). This field is valid when Last Descriptor (RDES0[8]) is set and either the Descriptor Error (RDES0[14]) or Overflow Error bits are are reset. The frame length also includes the two bytes appended to the Ethernet frame when IP checksum calculation (Type 1) is enabled and the received frame is not a MAC control frame.
This field is valid when Last Descriptor (RDES0[8]) is set. When the Last Descriptor and Error Summary bits are not set, this field indicates the accumulated number of
bytes that have been transferred for the current frame.
15
ES: Error Summary
Indicates the logical OR of the following bits:
This field is valid only when the Last Descriptor (RDES0[8]) is set.
14
DE: Descriptor Error
When set, this bit indicates a frame truncation caused by a frame that does not fit within the current descriptor buffers, and that the DMA does not own the Next
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Descriptor. The frame is truncated. This field is valid only when the Last Descriptor (RDES0[8]) is set
13
SAF: Source Address Filter Fail
When set, this bit indicates that the SA field of frame failed the SA Filter in the GMAC Core.
12
LE: Length Error
When set, this bit indicates that the actual length of the frame received and that the
Length/ Type field does not match. This bit is valid only when the Frame Type (RDES0[5]) bit is reset. Length error status is not valid when CRC error is present.
11
OE: Overflow Error
When set, this bit indicates that the received frame was damaged due to buffer overflow.
10
VLAN: VLAN Tag
When set, this bit indicates that the frame pointed to by this descriptor is a VLAN frame tagged by the GMACCore.
9
FS: First Descriptor
When set, this bit indicates that this descriptor contains the first buffer of the frame. If the size of the first buffer is 0, the second buffer contains the beginning of the frame. If the size of the second buffer is also 0, the next Descriptor contains the
beginning of the frame.
8
LS: Last Descriptor
When set, this bit indicates that the buffers pointed to by this descriptor are the last buffers of the frame.
7
IPC Checksum Error/Giant Frame
When IP Checksum Engine is enabled, this bit, when set, indicates that the 16-bit
IPv4 Header checksum calculated by the core did not match the received checksum bytes. The Error Summary bit[15] is NOT set when this bit is set in this mode.
6
LC: Late Collision
When set, this bit indicates that a late collision has occurred while receiving the frame in Half-Duplex mode.
5
FT: Frame Type
When set, this bit indicates that the Receive Frame is an Ethernet-type frame (the LT field is greater than or equal to 16’h0600). When this bit is reset, it indicates that the
received frame is an IEEE802.3 frame. This bit is not valid for Runt frames less than 14 bytes.
4
RWT: Receive Watchdog Timeout
When set, this bit indicates that the Receive Watchdog Timer has expired while
receiving the current frame and the current frame is truncated after the Watchdog Timeout.
3
RE: Receive Error
When set, this bit indicates that the gmii_rxer_i signal is asserted while gmii_rxdv_i is asserted during frame reception. This error also includes carrier extension error in GMII and Half-duplex mode. Error can be of less/no extension, or error (rxd ≠ 0f)
during extension.
2
DE: Dribble Bit Error
When set, this bit indicates that the received frame has a non-integer multiple of bytes (odd nibbles). This bit is valid only in MII Mode.
1
CE: CRC Error
When set, this bit indicates that a Cyclic Redundancy Check (CRC) Error occurred on the received frame. This field is valid only when the Last Descriptor (RDES0[8]) is set.
0
Rx MAC Address/Payload Checksum Error
When set, this bit indicates that the Rx MAC Address registers value (1 to 15) matched the frame’s DA field. When reset, this bit indicates that the Rx MAC Address Register 0 value matched the DA field.
If Full Checksum Offload Engine is enabled, this bit, when set, indicates the TCP, UDP,
or ICMP checksum the core calculated does not match the received encapsulated TCP, UDP, or ICMP segment’s Checksum field. This bit is also set when the received number
of payload bytes does not match the value indicated in the Length field of the encapsulated IPv4 or IPv6 datagram in the received Ethernet frame.
