Chapter 41 gmac ethernet Interface

Block Diagram

Fig. 41-1 GMAC architecture

The GMAC is broken up into multiple separate functional units. These blocks are interconnected in the MAC module. The block diagram shows the general flow of data and control signals between these blocks.
The GMAC transfers data to system memory through the AXI master interface. The host CPU uses the APB Slave interface to access the GMAC subsystem’s control and status registers (CSRs).

Only
The GMAC supports the PHY interfaces of reduced GMII (RGMII) and reduced MII (RMII).
The Transmit FIFO (Tx FIFO) buffers data read from system memory by the DMA before transmission by the GMAC Core. Similarly, the Receive FIFO (Rx FIFO) stores the Ethernet frames received from the line until they are transferred to system memory by the DMA. These are asynchronous FIFOs, as they also transfer the data between the application clock and the GMAC line clocks.

3. Function Description

   1. 
      T-chip
      Frame Structure

Data frames transmitted shall have the frame format shown in Fig 32-2.

Fig. 41-2 MAC Frame structure

The preamble
begins a frame transmission. The bit value of the preamble field consists of 7 octets with the following bit values:
10101010 10101010 10101010 10101010 10101010 10101010 10101010
The SFD (start frame delimiter) indicates the start of a frame and follows the preamble. The bit value is 10101011.
The data in a well formed frame shall consist of N octets data.

2. RMII Interface timing diagram

The Reduced Media Independent Interface (RMII) specification reduces the pin count between Ethernet PHYs and Switch ASICs (only in 10/100 mode). According to the IEEE 802.3u standard, an MII contains 16 pins for data and control. In devices incorporating multiple MAC or PHY interfaces (such as switches), the number of pins adds significant

cost with increase in port count. The RMII specification addresses this problem by reducing the pin count to 7 for each port - a 62.5% decrease in pin count.
The RMII module is instantiated between the GMAC and the PHY. This helps translation of the MAC’s MII into the RMII. The RMII block has the following characteristics:

• 
  Supports 10-Mbps and 100-Mbps operating rates. It does not support 1000-Mbps operation.
  
• 
  Two clock references are sourced externally or CRU, providing independent, 2-bit wide transmit and receive paths.
  

Transmit Bit Ordering

Only
Each nibble from the MII must be transmitted on the RMII a di-bit at a time with the order of di-bit transmission shown in Fig.1-3. The lower order bits (D1 and D0) are transmitted first followed by higher order bits (D2 and D3).


T-chip
Fig. 41-3 RMII transmission bit ordering