Chapter 41 gmac ethernet Interface

Management Interface

Only
The MAC management interface provides a simple, two-wire, serial interface to connect the GMAC and a managed PHY, for the purposes of controlling the PHY and gathering status from the PHY. The management interface consists of a pair of signals that transport the management information across the MII bus: MDIO and MDC.

T-chip
The GMAC initiates the management write/read operation. The clock gmii_mdc_o(MDC) is a divided clock fromthe application clock pclk_gmac. The divide factor depends on the clock range setting in the GMII address register. Clock range is set as follows:

Selection	pclk_gmac	MDC Clock
0000	60-100 MHz	pclk_gmac/42
0001	100-150 MHz	pclk_gmac/62
0010	20-35 MHz	pclk_gmac/16
0011	35-60 MHz	pclk_gmac/26
0100	150-250 MHz	pclk_gmac/102
0101	250-300 MHz	pclk_gmac/124
0110, 0111	Reserved

The MDC is the derivative of the application clock pclk_gmac. The management operation is performed through the gmii_mdi_i, gmii_mdo_o and gmii_mdo_o_e signals. A three-state buffer is implemented in the PAD.
The frame structure on the MDIO line is shown below.

Fig. 41-9 MDIO frame structure

IDLE: The mdio line is three-state; there is no clock on gmii_mdc_o PREAMBLE: 32 continuous bits of value 1
START: Start-of-frame is 2í01
OPCODE: 2’b10 for read and 2’b01 for write
PHY ADDR: 5-bit address select for one of 32 PHYs REG ADDR: Register address in the selected PHY
TA: Turnaround is 2’bZ0 for read and 2’b10 for Write
DATA: Any 16-bit value. In a write operation, the GMAC drives mdio; in a read operation, PHY drives it.

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