RMII Transmit Timing Diagrams
Fig.1-4 through 1-7 show MII-to-RMII transaction timing. The clk_rmii_i (REF_CLK) frequency is 50MHz in RMII interface. In 10Mb/s mode, as the REF_CLK frequency is 10 times as the data rate, the value on rmii_txd_o[1:0] (TXD[1:0]) shall be valid such that TXD[1:0] may be sampled every 10th cycle, regard-less of the starting cycle within the gRup and yield the correct frame data.
Fig. 41-4 Start of MII and RMII transmission in 100-Mbps mode
Fig. 41-5 End of MII and RMII Transmission in 100-Mbps Mode
Fig. 41-6 Start of MII and RMII Transmission in 10-Mbps Mode
Fig. 41-7 End of MII and RMII Transmission in 10-Mbps Mode
T-chip
Each nibble is transmitted to the MII from the di-bit received from the RMII in the nibble transmission order shown in Fig.1-8. The lower order bits (D0 and D1) are received first, followed by the higher order bits (D2 and D3).
Fig. 41-8 RMII receive bit ordering
The Reduced Gigabit Media Independent Interface (RGMII) specification reduces the pin count of the interconnection between the GMAC 10/100/1000 controller and the PHY for GMII and MII interfaces. To achieve this, the data path and control signals are reduced and multiplexed together with both the edges of the transmit and receive clocks. For gigabit operation the clocks operate at 125 MHz; for 10/100 operation, the clock rates are 2.5 MHz/25 MHz.
In the GMAC 10/100/1000 controller, the RGMII module is instantiated between the GMAC core’s GMII and the PHY to translate the control and data signals between the GMII and RGMII protocols.
The RGMII block has the following characteristics:
Supports 10-Mbps, 100-Mbps, and 1000-Mbps operation rates.
For the RGMII block, no extra clock is required because both the edges of the incoming clocks are used.
The RGMII block extracts the in-band (link speed, duplex mode and link status) status signals from the PHY and provides them to the GMAC core logic for link detection.
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