Chapter 41 gmac ethernet Interface

Transmit Descriptor 2 (TDES2)

TDES2 contains the address pointer to the first buffer of the descriptor.
Table 41-9 Transmit Descriptor 2

Bit	Description
31:0	Buffer 1 Address Pointer These bits indicate the physical address of Buffer 1. There is no limitation on the buffer address alignment.

Transmit Descriptor 3 (TDES3)

TDES3 contains the address pointer either to the second buffer of the descriptor or the next descriptor.
Table 41-10 Transmit Descriptor 3

Bit

Description

31:0

Buffer 2 Address Pointer (Next Descriptor Address) Indicates the physical address of Buffer 2 when a descriptor ring structure is used. If the Second Address Chained (TDES1[24]) bit is set, this address contains the pointer to the physical memory where the Next Descriptor is present. The buffer address pointer must be aligned to the bus width only when TDES1[24] is set. (LSBs are ignored internally.)

4. 
   Only
   Programming Guide

DMA Initialization – Descriptors

The following operations must be performed to initialize the DMA.

1. 
   Provide a software reset. This will reset all of the GMAC internal registers and logic. (GMAC_OP_MODE[0]).
   
2. 
   
   T-chip
   Wait for the completion of the reset process (poll GMAC_OP_MODE[0], which is only cleared after the reset operation is completed).
   
3. 
   Program the following fields to initialize the Bus Mode Register by setting values in register GMAC_BUS_MODE
   
   1. 
      Mixed Burst and AAL
      
   2. 
      Fixed burst or undefined burst
      
   3. 
      Burst length values and burst mode values.
      
   4. 
      Descriptor Length (only valid if Ring Mode is used)
      
   5. 
      Tx and Rx DMA Arbitration scheme
      
4. 
   Program the AXI Interface options in the register GMAC_BUS_MODE
   
   1. 
      If fixed burst-length is enabled, then select the maximum burst-length possible on the AXI bus (Bits[7:1])
      
5. 
   A proper descriptor chain for transmit and receive must be created. It should also ensure that the receive descriptors are owned by DMA (bit 31 of descriptor should be set). When OSF mode is used, at least two descriptors are required.
   
6. 
   Software should create three or more different transmit or receive descriptors in the chain before reusing any of the descriptors.
   
7. 
   Initialize receive and transmit descriptor list address with the base address of transmit and receive descriptor (register GMAC_RX_DESC_LIST_ADDR and GMAC_TX_DESC_LIST_ADDR).
   
8. 
   Program the following fields to initialize the mode of operation by setting values in register
   

GMAC_OP_MODE

1. 
   Receive and Transmit Store And Forward
   
2. 
   Receive and Transmit Threshold Control (RTC and TTC)
   
3. 
   Hardware Flow Control enable
   
4. 
   Flow Control Activation and De-activation thresholds for MTL Receive and Transmit FIFO (RFA and RFD)
   
5. 
   Error Frame and undersized good frame forwarding enable
   
6. 
   OSF Mode
   
1. 
   Clear the interrupt requests, by writing to those bits of the status register (interrupt bits only) which are set. For example, by writing 1 into bit 16 - normal interrupt summary will clear this bit (register GMAC_STATUS).
   
2. 
   Enable the interrupts by programming the interrupt enable register GMAC_INT_ENA.
   
3. 
   Start the Receive and Transmit DMA by setting SR (bit 1) and ST (bit 13) of the control register GMAC_OP_MODE.