Chapter 41 gmac ethernet Interface

Normal Receive and Transmit Operation

For normal operation, the following steps can be followed.

• 
  For normal transmit and receive interrupts, read the interrupt status. Then poll the descriptors, reading the status of the descriptor owned by the Host (either transmit or receive).
  
• 
  On completion of the above step, set appropriate values for the descriptors, ensuring that transmit and receive descriptors are owned by the DMA to resume the transmission and reception of data.
  
• 
  If the descriptors were not owned by the DMA (or no descriptor is available), the DMA will go into SUSPEND state. The transmission or reception can be resumed by freeing the descriptors and issuing a poll demand by writing 0 into the Tx/Rx poll demand register (GMAC_TX_POLL_DEMAND and GMAC_RX_POLL_DEMAND).
  
• 
  
  Only
  The values of the current host transmitter or receiver descriptor address pointer can be read for the debug process (GMAC_CUR_HOST_TX_DESC and GMAC_CUR_HOST_RX_DESC).
  
• 
  The values of the current host transmit buffer address pointer and receive buffer address pointer can be read for the debug process (GMAC_CUR_HOST_TX_Buf_ADDR and GMAC_CUR_HOST_RX_BUF_ADDR).
  

Stop and Start Operation

T-chip
When the transmission is required to be paused for some time then the following steps can be followed.

1. 
   Disable the Transmit DMA (if applicable), by clearing ST (bit 13) of the control register GMAC_OP_MODE.
   
2. 
   Wait for any previous frame transmissions to complete. This can be checked by reading the appropriate bits of MAC Debug register.
   
3. 
   Disable the MAC transmitter and MAC receiver by clearing the bits Transmit enable (TE bit-3) and Receive Enable (RE bit-2) in egister GMAC_MAC_CONF.
   
4. 
   Disable the Receive DMA (if applicable), after making sure the data in the RX FIFO is transferred to the system memory (by reading the register GMAC_DEBUG).
   
5. 
   Make sure both the TX FIFO and RX FIFO are empty.
   
6. 
   To re-start the operation, start the DMAs first, before enabling the MAC Transmitter and Receiver.
   

5.