Goal To emulate different simulation techniques using vhdl and compare them to one another and to an actual chip based design. (Use 12-pt font size.) Purpose

An Honors Thesis Proposal

Simulations of VHDL Circuits

Author: David Swan

Advisor: Abul Khondker

March 7, 2005

Goal

To emulate different simulation techniques using VHDL and compare them to one another and to an actual chip based design. (Use 12-pt font size.)

Purpose

VHSIC Hardware Description Language (VHDL) was developed by the Department of Defense as means to conduct research on integrated circuits. VHDL simulation is very useful to many engineers. It can help to produce a single chip design in a small scale operation. With little work and cost a file can easily be created that will emulate the desired circuit. One chip can easily be designed and created. In VHDL there are many different techniques to design and build a circuit. They differ by the process of how each is written. The data is saved differently and the connections are described differently. Because of these different techniques, different chip layouts and outputs are created. This causes different chip characteristics. Comparing these techniques can help to aid designers in what technique to choose for different purposes. VHDL simulations are very popular because of their cheap cost and testing abilities.

Background

There are many different VHDL simulation software products on the market. The one that I will most likely be using is from the Xilinx family of products. They provide MultiSim and other simulation programs and hardware that can easily turn a few lines of software code into an integrated circuit chip. Clarkson University does most of its work with this company so most of the equipment and software that has been used and what we currently have is from this company.

VHDL is a high level hardware description language. It has many components. It can compile, simulate, and synthesize certain circuits. VHDL is not the only hardware description language. There is also ABEL and many others. This research will be focusing on VHDL. The software package that will be used has incorporated simulators and test benches. The purpose of this is to see the timing diagrams and output waves of the outputs based on given inputs. This will help to calculate different delay values and be used to compare different designs and the final chip outputs.
Synthesizing is the conversion of the VHDL source files to files that are used to program chips. The Generic Array Logic (GAL) devices that I will most likely be using are either going to be programmable logic devices (PLD’s) or field programmable gate arrays (FPGA’s).These chips will have the final outputs. I will then put these through a series of yet to be developed tests to compare them to the expected output characteristics that were seen using a VHDL test bench.
Test Benches are used to test the outputs characteristics of a given set of VHDL files. They can be used by the designer to see if the desired output is achieved. The test bench will simulate the circuit based on the input files. This is very useful with small changes to a file. It will show the designer that the whole chip is working properly and that it can then be synthesized and placed in a PLD or FPGA.
A PLD is a rewritable device that has many possible interconnections. The layout is similar to that of a weaved basket. There are many possible connections that are overlapped with each other. When a file is written to simulate a circuit, it is synthesized and then another file is created that describes what interconnections are created. A FPGA is a large scale PLD.
In VHDL there are many different ways to do the same thing. Just a simple AND gate can be created using 5 or more different techniques. Some of these ways are easier to write while others may take up more space on a PLD or FPGA. The technique that should be used is different for many different cases. This is why it is important to understand each description, its advantages and disadvantages.
A simple Arithmetic Logic Unit (ALU) is a prime example of how different VHDL techniques can work together. Each part of the ALU can be created using different techniques based on the specific need. Below is a diagram of an ALU with 4 different functions.

These functions are AND, OR, XOR, and NOR. The inputs of the ALU are A and B. The selection of which operation is performed is selected by the S0 and S1 inputs. The And portion of the ALU was created using conditional statements. The code for this is shown below.

Library IEEE;

USE IEEE.std_logic_1164.all;

ENTITY AND2 IS

PORT (

ANDA : IN std_logic;

ANDB : IN std_logic;

ANDOUT : OUT std_logic

);

END AND2 ;

ARCHITECTURE AND2_conditional OF AND2 IS

BEGIN

ANDOUT <= '1' after 6.6 ns when ANDA = '1' and ANDB = '1' else '0';

END AND2_conditional;

The OR gate was created using selected signal assignments. Conditional signal assignment statements encorporate the words when and else. It is very similar to a C style of programming. It is very usefull when converting a large table of input values to a specified table of output values. The code for this is shown below.
Library IEEE;

USE IEEE.std_logic_1164.all;

ENTITY OR2 IS

PORT (

ORA : IN std_logic;

ORB : IN std_logic;

OROUT : OUT std_logic

);

END OR2 ;

ARCHITECTURE OR2_selected OF OR2 IS

SIGNAL COMBO : std_logic_vector ( 1 DOWNTO 0);

BEGIN

COMBO <= ORA & ORB ;

with COMBO select

OROUT <= '1' after 18 ns when "01",

'1' after 18 ns when "10",

'1' after 18 ns when "11",

'0' after 18 ns when others;

END OR2_selected;

The XOR gate was created using a behavioral description with a process statement. Behavioral Design incorporates different process that can be executed in parallel with each other. These concurrent statements are the basis behind the behavioral design. What might have taken 10 lines can now be piped into one. The code is shown below.

Library IEEE;

USE IEEE.std_logic_1164.all;

ENTITY XOR2 IS

PORT (

XORA : IN std_logic;

XORB : IN std_logic;

XOROUT : OUT std_logic

);

END XOR2 ;

ARCHITECTURE XOR2_behavioral OF XOR2 IS

BEGIN

process(XORA, XORB)

variable X: std_logic ;

BEGIN

X := XORA xor XORB;

XOROUT <= X after 30 ns;

end process ;

END XOR2_behavioral;
The inverter was created using dataflow. Dataflow Design is a style of writing VHDL that describes the data flowing between different parts of the circuit. With data flow it is easy to include statements such as when, and, if, or, and not. The code for this is shown below.
Library IEEE;

USE IEEE.std_logic_1164.all;

ENTITY INV1 IS

PORT (

INV1 : IN std_logic;

INVOUT : OUT std_logic

);

END INV1 ;

ARCHITECTURE INV1_dataflow OF INV1 IS

BEGIN

INVOUT <= not INV1 after 22 ns;

END INV1_dataflow;

The final ALU is put together using structural VHDL techniques. Structural Design is one of the most common techniques in writing VHDL code. This is the most equivalent to a given schematic of a circuit. The whole basis is to declare the interconnections between given ports and signals. Structural is used most often when using many different components to build a certain circuit. The input and output ports of these components are defined and then a port map is used to connect the ports. An example is given below.
Library IEEE;

USE IEEE.std_logic_1164.all;

ENTITY ALU IS

PORT (

SALU : IN std_logic_vector (1 DOWNTO 0);

A, B: IN std_logic;

DALU : OUT std_logic

);

END ALU ;

ARCHITECTURE ALU_structural OF ALU IS

COMPONENT AND2

PORT (

ANDA : IN std_logic;

ANDB : IN std_logic;

ANDOUT : OUT std_logic

);

END COMPONENT ;

COMPONENT OR2

PORT (

ORA : IN std_logic;

ORB : IN std_logic;

OROUT : OUT std_logic

);

END COMPONENT ;

COMPONENT XOR2

PORT (

XORA : IN std_logic;

XORB : IN std_logic;

XOROUT : OUT std_logic

);

END COMPONENT ;

COMPONENT INV1

PORT (

INV1 : IN std_logic;

INVOUT : OUT std_logic

);

END COMPONENT ;

COMPONENT mux4in1b

PORT (

S : IN std_logic_vector (1 DOWNTO 0);

C0, C1, C2, C3: IN std_logic;

D : OUT std_logic

);

END COMPONENT ;

SIGNAL Wire : std_logic_vector ( 3 DOWNTO 0 );
BEGIN

U0_AND2: AND2 PORT MAP (ANDA => A, ANDB => B, ANDOUT => Wire(0));

U1_OR2: OR2 PORT MAP (ORA => A, ORB => B, OROUT => Wire(1));

U2_XOR2: XOR2 PORT MAP (XORA => A, XORB => B, XOROUT => Wire(2));

U3_INV1: INV1 PORT MAP (INV1 => A, INVOUT => Wire(3));

U4_mux4in1b: mux4in1b PORT MAP ( C0 => Wire(0), C1 => Wire(1), C2 => Wire(2), C3 => Wire(3), S(0) => SALU(0), S(1) => SALU(1), D => DALU);

This was a very simple example of the different techniques of writing VHDL code. Each technique when synthesized will create different interconnects in the final hardware output. My research will try and focus on these different interconnects and the advantages and disadvantages of each.

Preliminary Work

I have been using the Xilinx software package for the past year. I have a firm understanding of most of the different techniques and have already synthesized a few designs. I have already created a bunch of files of different gates that I created using the different techniques. I feel very comfortable with the software. I feel that once I synthesize a few more designs that I will be able to handle transferring the design to a PLD or FPGA as well.

I am continuing to research what has been previously done in VHDL. I hope to find something that someone else has done and go one step further and improve upon their findings.
TimeTable

Date	Goals
March 7, 2005	Complete the Proposal and meet with my advisor every week to better define my problem.
Mid April 2005	Have my Proposal Well defined and start focusing on my problem. Also to continue Researching my problem to see what else is happening.
Summer 2005	Continue Researching and start to develop some VHDL files that I can use to conduct my research.
Fall 2005	Synthesize my designs and place them on a PLD or FPGA. Start to get timing data and do the statistical analysis.
Spring 2006	Finish up the Analysis. Write The Thesis and Give my presentation.

References

[1] Froessl, Juergen, Kropf, Thomas, “New model to uniformly represent the function and timing of MOS circuits and its application to VHDL simulation”, Proceedins of the European Design and Test Conference, 1994, 343-348

[2] Wall, R.W., Wall, L.R., “Generating Verifiable Microprocessors State Machine Code with HDL Design Tools”, IECON Porceedings, v 3, 2003, 2441-2446
[3] McHenry, John T., Midkiff, Scott F. “VHDL modeling for the performance evaluation of multicomputer networks”, Proceedings of the IEEE International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, 1992, 174-178
[4] Wackerly, John F., 2001 Digital Design Principles and Practices, Upper Saddle River: Prentice Hall