Chapter 41 gmac ethernet Interface



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Bit

Attr

Reset Value

Description

31:0


RW


0x00000000



STL
Start of Transmit List
This field contains the base address of the First Descriptor in the Transmit Descriptor list. The LSB bits [1/2/3:0] for 32/64/128-bit bus width) will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are
Read Only.




T-chip
GMAC_STATUS


Address: Operational Base + offset (0x1014) Status Register

Bit

Attr

Reset Value

Description

31:29

RO

0x0

reserved

28

RO

0x0

GPI
GMAC PMT Interrupt
This bit indicates an interrupt event in the GMAC core's PMT module. The software must read the corresponding registers in the GMAC core to get the exact cause of interrupt and clear its source to reset this bit to 1'b0. The interrupt signal from the GMAC subsystem (sbd_intr_o) is high when this bit is high.


Only

T-chip



Bit

Attr

Reset Value

Description

27

RO

0x0

GMI
GMAC MMC Interrupt
This bit reflects an interrupt event in the MMC module of the GMAC core. The software must read the corresponding registers in the GMAC core to get the exact cause of interrupt and clear the source of interrupt to make this bit as 1'b0. The interrupt signal from the GMAC subsystem (sbd_intr_o) is high when this bit
is high.

26

RO

0x0

GLI
GMAC Line interface Interrupt
This bit reflects an interrupt event in the GMAC Core's PCS or RGMII interface block. The software must read the corresponding registers in the GMAC core to get the exact cause of interrupt and clear the source of interrupt to make this bit as 1'b0. The interrupt signal from the GMAC subsystem (sbd_intr_o) is high when this bit is high.

25:23


RO


0x0


EB
Error Bits
These bits indicate the type of error that caused a Bus Error (e.g., error response on the AXI interface). Valid only with Fatal Bus Error bit (Register GMAC_STATUS[13]) set. This field does not generate an interrupt.
Bit 23: 1'b1 Error during data transfer by TxDMA
1'b0 Error during data transfer by RxDMA
Bit 24: 1'b1 Error during read transfer 1'b0 Error during write transfer
Bit 25: 1'b1 Error during descriptor access
1'b0 Error during data buffer access


Only

T-chip




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