TTC
Transmit Threshold Control
These three bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when the TSF bit (Bit 21) is reset. 3'b000: 64
3'b001: 128
3'b010: 192
3'b011: 256
3'b100: 40
3'b101: 32
3'b110: 24
3'b111: 16
Only
T-chip
Bit
Attr
ResetValue
Description
13
RW
0x0
ST
Start/Stop Transmission Command
When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by Register GMAC_TX_DESC_LIST_ADDR, or from the position retained when transmission was stopped previously. If the current descriptor is not owned by the DMA, transmission enters the Suspended state and Transmit Buffer Unavailable (Register GMAC_STATUS[2]) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting DMA Register TX_DESC_LIST_ADDR, then the DMA behavior is unpredictable.
When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and becomes the current position when transmission is restarted. The stop transmission command is effective only the transmission of the current frame is complete or when the transmission is
in the Suspended state.
12:11
RW
0x0
RFD
Threshold for deactivating flow control (in both HD and FD)
These bits control the threshold (Fill-level of Rx FIFO) at which the flow-control is deasserted after activation.
2'b00: Full minus 1 KB 2'b01: Full minus 2 KB 2'b10: Full minus 3 KB 2'b11: Full minus 4 KB
Note that the deassertion is effective only
after flow control is asserted.
