Ladder Logic (lad) for S7-300 and S7-400 Programming
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Description ---( SS ) (Retentive On-Delay Timer Coil) starts the specified timer if there is a positive edge on the RLO state. The signal state of the timer is "1" if the time value has elapsed. A restart of the timer is only possible if it is reset explicitly. Only a reset causes the signal state of the timer to be set to "0". The timer restarts with the specified time value if the RLO changes from "0" to "1" while the timer is running. See also "Location of a Timer in Memory and Components of a Timer" and S_ODTS (Retentive On-Delay S5 Timer). Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: - - - - - 0 - - 0 Timer Instructions 13.11 ---( SS ) Retentive On-Delay Timer Coil Ladder Logic (LAD) for S7-300 and S7-400 Programming 174 Reference Manual, 04/2017, A5E41524738-AA Example Network 3 Network 2 Network 1 I 0.0 SS T5 T5 Q A.0 S5T#2S I 0.1 T5 R If the signal state of input I0.0 changes from "0" to "1" (positive edge in RLO), the timer T5 is started. If the signal state of input I0.0 changes from "0" to "1" before the timer has expired, the timer is re-triggered. The output Q4.0 will be "1" if the timer elapsed. A signal state "1" at input I0.1 will reset timer T5, which stops the timer and clears the remaining portion of the time value to "0". Timer Instructions 13.12 ---( SF ) Off-Delay Timer Coil Ladder Logic (LAD) for S7-300 and S7-400 Programming Reference Manual, 04/2017, A5E41524738-AA 175 13.12 ---( SF ) Off-Delay Timer Coil Symbol English German ---( SF ) ---( SA ) Timer Instructions 13.12 ---( SF ) Off-Delay Timer Coil Ladder Logic (LAD) for S7-300 and S7-400 Programming 176 Reference Manual, 04/2017, A5E41524738-AA If the signal state of input I0.0 changes from "1" to "0" the timer is started. The signal state of output Q4.0 is "1" when input I0.0 is "1" or the timer is running. A signal state change from "0" to "1" at input I0.1 will reset timer T5 which stops the timer and clears the remaining portion of the time value to "0". Ladder Logic (LAD) for S7-300 and S7-400 Programming Reference Manual, 04/2017, A5E41524738-AA 177 14 Word Logic Instructions 14.1 Overview of Word logic instructions Description Word logic instructions compare pairs of words (16 bits) and double words (32 bits) bit by bit, according to Boolean logic. If the result at output OUT does not equal 0, bit CC 1 of the status word is set to "1". If the result at output OUT does equal 0, bit CC 1 of the status word is set to "0". The following word logic instructions are available: • WAND_W (Word) AND Word • WOR_W (Word) OR Word • WXOR_W (Word) Exclusive OR Word • WAND_DW (Word) AND Double Word • WOR_DW (Word) OR Double Word • WXOR_DW (Word) Exclusive OR Double Word Word Logic Instructions 14.2 WAND_W (Word) AND Word Ladder Logic (LAD) for S7-300 and S7-400 Programming 178 Reference Manual, 04/2017, A5E41524738-AA 14.2 WAND_W (Word) AND Word Symbol WAND_W EN ENO IN2 OUT IN1 Parameter Data Type Memory Area Description EN BOOL I, Q, M, L, D Enable input ENO BOOL I, Q, M, L, D Enable output IN1 WORD I, Q, M, L, D First value for logic operation IN2 WORD I, Q, M, L, D Second value for logic operation OUT WORD I, Q, M, L, D Result word of logic operation Description WAND_W (AND Words) is activated by signal state "1" at the enable (EN) input and ANDs the two word values present at IN1 and IN2 bit by bit. The values are interpreted as pure bit patterns. The result can be scanned at the output OUT. ENO has the same logic state as EN. Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: 1 x 0 0 - x 1 1 1 Example WAND_W IN2 IN1 EN MW0 MW2 Q 4.0 I 0.0 2#0000000000001111 ENO OUT The instruction is executed if I0.0 is "1". Only bits 0 to 3 of MW0 are relevant, the rest of MW0 is masked by the IN2 word bit pattern: MW0 = 01010101 01010101 IN2 = 00000000 00001111 MW0 AND IN2 = MW2 = 00000000 00000101 Q4.0 is "1" if the instruction is executed. Word Logic Instructions 14.3 WOR_W (Word) OR Word Ladder Logic (LAD) for S7-300 and S7-400 Programming Reference Manual, 04/2017, A5E41524738-AA 179 14.3 WOR_W (Word) OR Word Symbol WOR_W EN ENO IN2 OUT IN1 Parameter Data Type Memory Area Description EN BOOL I, Q, M, L, D Enable input ENO BOOL I, Q, M, L, D Enable output IN1 WORD I, Q, M, L, D First value for logic operation IN2 WORD I, Q, M, L, D Second value for logic operation OUT WORD I, Q, M, L, D Result word of logic operation Description WOR_W (OR Words) is activated by signal state "1" at the enable (EN) input and ORs the two word values present at IN1 and IN2 bit by bit. The values are interpreted as pure bit patterns. The result can be scanned at the output OUT. ENO has the same logic state as EN. Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: 1 x 0 0 - x 1 1 1 Example WOR_W IN2 IN1 EN MW0 MW2 Q 4.0 I 0.0 2#0000000000001111 ENO OUT The instruction is executed if I0.0 is "1". Bits 0 to 3 are set to "1", all other MW0 bits are not changed. MW0 = 01010101 01010101 IN2 = 00000000 00001111 MW0 OR IN2=MW2 = 01010101 01011111 Q4.0 is "1" if the instruction is executed. Word Logic Instructions 14.4 WAND_DW (Word) AND Double Word Ladder Logic (LAD) for S7-300 and S7-400 Programming 180 Reference Manual, 04/2017, A5E41524738-AA 14.4 WAND_DW (Word) AND Double Word Symbol WAND_DW EN ENO IN2 OUT IN1 Parameter Data Type Memory Area Description EN BOOL I, Q, M, L, D Enable input ENO BOOL I, Q, M, L, D Enable output IN1 DWORD I, Q, M, L, D First value for logic operation IN2 DWORD I, Q, M, L, D Second value for logic operation OUT DWORD I, Q, M, L, D Result double word of logic operation Description WAND_DW (AND Double Words) is activated by signal state "1" at the enable (EN) input and ANDs the two word values present at IN1 and IN2 bit by bit. The values are interpreted as pure bit patterns. The result can be scanned at the output OUT. ENO has the same logic state as EN. Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: 1 x 0 0 - x 1 1 1 Example WAND_DW IN2 IN1 EN MD0 MD4 Q 4.0 I 0.0 DW#16#FFF ENO OUT The instruction is executed if I0.0 is "1". Only bits 0 and 11 of MD0 are relevant, the rest of MD0 is masked by the IN2 bit pattern: MD0 = 01010101 01010101 01010101 01010101 IN2 = 00000000 00000000 00001111 11111111 MD0 AND IN2 = MD4 = 00000000 00000000 00000101 01010101 Q4.0 is "1" if the instruction is executed. Word Logic Instructions 14.5 WOR_DW (Word) OR Double Word Ladder Logic (LAD) for S7-300 and S7-400 Programming Reference Manual, 04/2017, A5E41524738-AA 181 14.5 WOR_DW (Word) OR Double Word Symbol WOR_DW EN ENO IN2 OUT IN1 Parameter Data Type Memory Area Description EN BOOL I, Q, M, L, D Enable input ENO BOOL I, Q, M, L, D Enable output IN1 DWORD I, Q, M, L, D First value for logic operation IN2 DWORD I, Q, M, L, D Second value for logic operation OUT DWORD I, Q, M, L, D Result double word of logic operation Description WOR_DW (OR Double Words) is activated by signal state "1" at the enable (EN) input and ORs the two word values present at IN1 and IN2 bit by bit. The values are interpreted as pure bit patterns. The result can be scanned at the output OUT. ENO has the same logic state as EN. Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: 1 x 0 0 - x 1 1 1 Example WOR_DW IN2 IN1 EN MD0 MD4 Q 4.0 I 0.0 DW#16#FFF ENO OUT The instruction is executed if I0.0 is "1". Bits 0 to 11 are set to "1", the remaining MD0 bits are not changed: MD0 = 01010101 01010101 01010101 01010101 IN2 = 00000000 00000000 00001111 11111111 MD0 OR IN2 = MD4 = 01010101 01010101 01011111 11111111 Q4.0 is "1" if the instruction is executed. Word Logic Instructions 14.6 WXOR_W (Word) Exclusive OR Word Ladder Logic (LAD) for S7-300 and S7-400 Programming 182 Reference Manual, 04/2017, A5E41524738-AA 14.6 WXOR_W (Word) Exclusive OR Word Symbol WXOR_W EN ENO IN2 OUT IN1 Parameter Data Type Memory Area Description EN BOOL I, Q, M, L, D Enable input ENO BOOL I, Q, M, L, D Enable output IN1 WORD I, Q, M, L, D First value for logic operation IN2 WORD I, Q, M, L, D Second value for logic operation OUT WORD I, Q, M, L, D Result word of logic operation Description WXOR_W (Exclusive OR Word) is activated by signal state "1" at the enable (EN) input and XORs the two word values present at IN1 and IN2 bit by bit. The values are interpreted as pure bit patterns. The result can be scanned at the output OUT. ENO has the same logic state as EN. Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: 1 x 0 0 - x 1 1 1 Example WXOR_W IN2 IN1 EN MW0 MW2 Q 4.0 I 0.0 2#0000000000001111 ENO OUT The instruction is executed if I0.0 is "1": MW0 = 01010101 01010101 IN2 = 00000000 00001111 MW0 XOR IN2 = MW2 = 01010101 01011010 Q4.0 is "1" if the instruction is executed. Word Logic Instructions 14.7 WXOR_DW (Word) Exclusive OR Double Word Ladder Logic (LAD) for S7-300 and S7-400 Programming Reference Manual, 04/2017, A5E41524738-AA 183 14.7 WXOR_DW (Word) Exclusive OR Double Word Symbol WXOR_DW EN ENO IN2 OUT IN1 Parameter Data Type Memory Area Description EN BOOL I, Q, M, L, D Enable input ENO BOOL I, Q, M, L, D Enable output IN1 DWORD I, Q, M, L, D First value for logic operation IN2 DWORD I, Q, M, L, D Second value for logic operation OUT DWORD I, Q, M, L, D Result double word of logic operation Description WXOR_DW (Exclusive OR Double Word) is activated by signal state "1" at the enable (EN) input and XORs the two word values present at IN1 and IN2 bit by bit. The values are interpreted as pure bit patterns. The result can be scanned at the output OUT. ENO has the same logic state as EN. Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: 1 x 0 0 - x 1 1 1 Example WXOR_DW IN2 IN1 EN MD0 MD4 Q 4.0 I 0.0 DW#16#FFF ENO OUT The instruction is executed if I0.0 is "1": MD0 = 01010101 01010101 01010101 01010101 IN2 = 00000000 00000000 00001111 11111111 MW2 = MD0 XOR IN2 = 01010101 01010101 01011010 10101010 Q4.0 is "1" if the instruction is executed. Word Logic Instructions 14.7 WXOR_DW (Word) Exclusive OR Double Word Ladder Logic (LAD) for S7-300 and S7-400 Programming 184 Reference Manual, 04/2017, A5E41524738-AA Ladder Logic (LAD) for S7-300 and S7-400 Programming Reference Manual, 04/2017, A5E41524738-AA 185 A Overview of All LAD Instructions A.1 LAD Instructions Sorted According to English Mnemonics (International) English Mnemonics German Mnemonics Program Elements Catalog Description ---| |--- ---| |--- Bit logic Instruction Normally Open Contact (Address) ---|/|--- ---|/|--- Bit logic Instruction Normally Closed Contact (Address) ---( ) ---( ) Bit logic Instruction Output Coil ---(#)--- ---(#)--- Bit logic Instruction Midline Output ==0 ---| |--- ==0 ---| |--- Status bits Result Bit Equal 0 >0 ---| |--- >0 ---| |--- Status bits Result Bit Greater Than 0 >=0 ---| |--- >=0 ---| |--- Status bits Result Bit Greater Equal 0 <=0 ---| |--- <=0 ---| |--- Status bits Result Bit Less Equal 0 <0 ---| |--- <0 ---| |--- Status bits Result Bit Less Than 0 <>0 ---| |--- <>0 ---| |--- Status bits Result Bit Not Equal 0 ABS ABS Floating point Instruction Establish the Absolute Value of a Floating-Point Number ACOS ACOS Floating point Instruction Establish the Arc Cosine Value ADD_DI ADD_DI Integer Math Instruction Add Double Integer ADD_I ADD_I Integer Math Instruction Add Integer ADD_R ADD_R Floating point Instruction Add Real ASIN ASIN Floating point Instruction Establish the Arc Sine Value ATAN ATAN Floating point Instruction Establish the Arc Tangent Value BCD_DI BCD_DI Convert BCD to Double Integer BCD_I BCD_I Convert BCD to Integer BR ---| |--- BIE ---| |--- Status bits Exception Bit Binary Result ----(CALL) ----(CALL) Program control Call FC SFC from Coil (without Parameters) CALL_FB CALL_FB Program control Call FB from Box CALL_FC CALL_FC Program control Call FC from Box CALL_SFB CALL_SFB Program control Call System FB from Box CALL_SFC CALL_SFC Program control Call System FC from Box ----(CD) ----(ZR) Counters Down Counter Coil CEIL CEIL Convert Ceiling CMP >=D CMP >=D Compare Compare Double Integer (==, <>, >, <, >=, <=) CMP >=I CMP >=I Compare Compare Integer (==, <>, >, <, >=, <=) Overview of All LAD Instructions A.1 LAD Instructions Sorted According to English Mnemonics (International) Ladder Logic (LAD) for S7-300 and S7-400 Programming 186 Reference Manual, 04/2017, A5E41524738-AA English Mnemonics German Mnemonics Program Elements Catalog Description CMP >=R CMP >=R Compare Compare Real (==, <>, >, <, >=, <=) COS COS Floating point Instruction Establish the Cosine Value ----(CU) ---( ZV ) Counters Up Counter Coil DI_BCD DI_BCD Convert Double Integer to BCD DI_R DI_R Convert Double Integer to Floating-Point DIV_DI DIV_DI Integer Math Instruction Divide Double Integer DIV_I DIV_I Integer Math Instruction Divide Integer DIV_R DIV_R Floating point Instruction Divide Real EXP EXP Floating point Instruction Establish the Exponential Value FLOOR FLOOR Convert Floor I_BCD I_BCD Convert Integer to BCD I_DI I_DI Convert Integer to Double Integer INV_I INV_I Convert Ones Complement Integer INV_DI INV_DI Convert Ones Complement Double Integer ---(JMP) ---(JMP) Jumps Unconditional Jump ---(JMP) ---(JMP) Jumps Conditional Jump ---(JMPN) ---(JMPN) Jumps Jump-If-Not LABEL LABEL Jumps Label LN LN Floating point Instruction Establish the Natural Logarithm ---(MCR>) ---(MCR>) Program control Master Control Relay Off ---(MCR<) ---(MCR<) Program control Master Control Relay On ---(MCRA) ---(MCRA) Program control Master Control Relay Activate ---(MCRD) ---(MCRD) Program control Master Control Relay Deactivate MOD_DI MOD_DI Integer Math Instruction Return Fraction Double Integer MOVE MOVE Move Assign a Value MUL_DI MUL_DI Integer Math Instruction Multiply Double Integer MUL_I MUL_I Integer Math Instruction Multiply Integer MUL_R MUL_R Floating point Instruction Multiply Real ---( N )--- ---( N )--- Bit logic Instruction Negative RLO Edge Detection NEG NEG Bit logic Instruction Address Negative Edge Detection NEG_DI NEG_DI Convert Twos Complement Double Integer NEG_I NEG_I Convert Twos Complement Integer NEG_R NEG_R Convert Negate Floating-Point Number ---| NOT |--- ---| NOT |--- Bit logic Instruction Invert Power Flow ---( OPN ) ---( OPN ) DB call Open Data Block: DB or DI OS ---| |--- OS ---| |--- Status bits Exception Bit Overflow Stored Overview of All LAD Instructions A.1 LAD Instructions Sorted According to English Mnemonics (International) Ladder Logic (LAD) for S7-300 and S7-400 Programming Reference Manual, 04/2017, A5E41524738-AA 187 Yüklə 1,39 Mb. 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