Ladder Logic (lad) for S7-300 and S7-400 Programming
Yüklə 1,39 Mb. Pdf görüntüsü
|
|
Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: x x x x - x x x 1 Shift and Rotate Instructions 11.1 Shift Instructions Ladder Logic (LAD) for S7-300 and S7-400 Programming 132 Reference Manual, 04/2017, A5E41524738-AA Example SHL_W N IN EN MW0 MW4 Q 4.0 I 0.0 MW2 ENO OUT S The SHL_W box is activated by logic "1" at I0.0. MW0 is loaded and shifted left by the number of bits specified with MW2. The result is written to MW4. Q4.0 is set. Shift and Rotate Instructions 11.1 Shift Instructions Ladder Logic (LAD) for S7-300 and S7-400 Programming Reference Manual, 04/2017, A5E41524738-AA 133 11.1.5 SHR_W Shift Right Word Symbol SHR_W EN OUT N ENO IN Parameter Data Type Memory Area Description EN BOOL I, Q, M, L, D Enable input ENO BOOL I, Q, M, L, D Enable output IN WORD I, Q, M, L, D Value to shift N WORD I, Q, M, L, D Number of bit positions to shift OUT WORD I, Q, M, L, D Result word of shift instruction Description SHR_W (Shift Right Word) is activated by a logic "1" at the Enable (EN) Input. The SHR_W instruction is used to shift bits 0 to 15 of input IN bit by bit to the right. Bits 16 to 31 are not affected. The input N specifies the number of bits by which to shift. If N is larger than 16, the command writes a "0" at output OUT and sets the bits CC 0 and OV in the status word to "0". N zeros are also shifted in from the left to fill vacated bit positions. The result of the shift instruction can be scanned at output OUT. The CC 0 bit and the OV bit are set to "0" by SHR_W if N is not equal to 0. ENO has the same signal state as EN. Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: x x x x - x x x 1 Example SHR_W N IN EN MW0 MW4 Q 4.0 I 0.0 MW2 ENO OUT S The SHR_W box is activated by logic "1" at I0.0. MW0 is loaded and shifted right by the number of bits specified with MW2. The result is written to MW4. Q4.0 is set. Shift and Rotate Instructions 11.1 Shift Instructions Ladder Logic (LAD) for S7-300 and S7-400 Programming 134 Reference Manual, 04/2017, A5E41524738-AA 11.1.6 SHL_DW Shift Left Double Word Symbol SHL_DW EN OUT N ENO IN Parameter Data Type Memory Area Description EN BOOL I, Q, M, L, D Enable input ENO BOOL I, Q, M, L, D Enable output IN DWORD I, Q, M, L, D Value to shift N WORD I, Q, M, L, D Number of bit positions to shift OUT DWORD I, Q, M, L, D Result double word of shift instruction Description SHL_DW (Shift Left Double Word) is activated by a logic "1" at the Enable (EN) Input. The SHL_DW instruction is used to shift bits 0 to 31 of input IN bit by bit to the left. The input N specifies the number of bits by which to shift. If N is larger than 32, the command writes a "0" at output OUT and sets the bits CC 0 and OV in the status word to "0". N zeros are also shifted in from the right to fill vacated bit positions. The result double word of the shift instruction can be scanned at output OUT. The CC 0 bit and the OV bit are set to "0" by SHL_DW if N is not equal to 0. ENO has the same signal state as EN. Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: x x x x - x x x 1 Example SHL_DW N IN EN MD0 MD10 Q 4.0 I 0.0 MW4 ENO OUT S The SHL_DW box is activated by logic "1" at I0.0. MD0 is loaded and shifted left by the number of bits specified with MW4. The result is written to MD10. Q4.0 is set. Shift and Rotate Instructions 11.1 Shift Instructions Ladder Logic (LAD) for S7-300 and S7-400 Programming Reference Manual, 04/2017, A5E41524738-AA 135 11.1.7 SHR_DW Shift Right Double Word Symbol SHR_DW EN OUT N ENO IN Parameter Data Type Memory Area Description EN BOOL I, Q, M, L, D Enable input ENO BOOL I, Q, M, L, D Enable output IN DWORD I, Q, M, L, D Value to shift N WORD I, Q, M, L, D Number of bit positions to shift OUT DWORD I, Q, M, L, D Result double word of shift instruction Description SHR_DW (Shift Right Double Word) is activated by a logic "1" at the Enable (EN) Input. The SHR_DW instruction is used to shift bits 0 to 31 of input IN bit by bit to the right. The input N specifies the number of bits by which to shift. If N is larger than 32, the command writes a "0" at output OUT and sets the bits CC 0 and OV in the status word to "0". N zeros are also shifted in from the left to fill vacated bit positions. The result double word of the shift instruction can be scanned at output OUT. The CC 0 bit and the OV bit are set to "0" by SHR_DW if N is not equal to 0. ENO has the same signal state as EN. 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 IN 31... ...16 15... ...0 3 places N OUT 0 0 0 1 The vacated places are filled with zeros. These three bits are lost. Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: x x x x - x x x 1 Shift and Rotate Instructions 11.1 Shift Instructions Ladder Logic (LAD) for S7-300 and S7-400 Programming 136 Reference Manual, 04/2017, A5E41524738-AA Example SHR_DW N IN EN MD0 MD10 Q 4.0 I 0.0 MW4 ENO OUT S The SHR_DW box is activated by logic "1" at I0.0. MD0 is loaded and shifted right by the number of bits specified with MW4. The result is written to MD10. Q4.0 is set. Shift and Rotate Instructions 11.2 Rotate Instructions Ladder Logic (LAD) for S7-300 and S7-400 Programming Reference Manual, 04/2017, A5E41524738-AA 137 11.2 Rotate Instructions 11.2.1 Overview of Rotate Instructions Description You can use the Rotate instructions to rotate the entire contents of input IN bit by bit to the left or to the right. The vacated bit places are filled with the signal states of the bits that are shifted out of input IN. The number that you supply for input parameter N specifies the number of bits by which to rotate. Depending on the instruction, rotation takes place via the CC 1 bit of the status word. The CC 0 bit of the status word is reset to 0. The following rotate instructions are available: • ROL_DW Rotate Left Double Word • ROR_DW Rotate Right Double Word 11.2.2 ROL_DW Rotate Left Double Word0 Symbol ROL_DW EN OUT N ENO IN Parameter Data Type Memory Area Description EN BOOL I, Q, M, L, D Enable input ENO BOOL I, Q, M, L, D Enable output IN DWORD I, Q, M, L, D Value to rotate N WORD I, Q, M, L, D Number of bit positions to rotate OUT DWORD I, Q, M, L, D Result double word of rotate instruction Shift and Rotate Instructions 11.2 Rotate Instructions Ladder Logic (LAD) for S7-300 and S7-400 Programming 138 Reference Manual, 04/2017, A5E41524738-AA Description ROL_DW (Rotate Left Double Word) is activated by a logic "1" at the Enable (EN) Input. The ROL_DW instruction is used to rotate the entire contents of input IN bit by bit to the left. The input N specifies the number of bits by which to rotate. If N is larger than 32, the double word IN is rotated by ((N-1) modulo 32)+1 positions. The bit positions shifted in from the right are assigned the logic states of the bits which were rotated out to the left. The result double word of the rotate instruction can be scanned at output OUT. The CC 0 bit and the OV bit are set to "0" by ROL_DW if N is not equal to 0. ENO has the same signal state as EN. IN 1 1 1 1 0 0 0 0 1 0 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 1 0 31... ...16 15... ...0 3 places N OUT 1 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 The signal states of the three bits that are shifted out are inserted in the vacated places. These three bits are lost. Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: x x x x - x x x 1 Example ROL_DW N IN EN MD0 MD10 Q 4.0 I 0.0 MW4 ENO OUT S The ROL_DW box is activated by logic "1" at I0.0. MD0 is loaded and rotated to the left by the number of bits specified with MW4. The result is written to MD10. Q4.0 is set. Shift and Rotate Instructions 11.2 Rotate Instructions Ladder Logic (LAD) for S7-300 and S7-400 Programming Reference Manual, 04/2017, A5E41524738-AA 139 11.2.3 ROR_DW Rotate Right Double Word Symbol ROR_DW EN OUT N ENO IN Parameter Data Type Memory Area Description EN BOOL I, Q, M, L, D Enable input ENO BOOL I, Q, M, L, D Enable output IN DWORD I, Q, M, L, D Value to rotate N WORD I, Q, M, L, D Number of bit positions to rotate OUT DWORD I, Q, M, L, D Result double word of rotate instruction Description ROR_DW (Rotate Right Double Word) is activated by a logic "1" at the Enable (EN) Input. The ROR_DW instruction is used to rotate the entire contents of input IN bit by bit to the right. The input N specifies the number of bits by which to rotate. If N is larger than 32, the double word IN is rotated by ((N-1) modulo 32)+1 positions. The bit positions shifted in from the left are assigned the logic states of the bits which were rotated out to the right. The result double word of the rotate instruction can be scanned at output OUT. The CC 0 bit and the OV bit are set to "0" by ROR_DW if N is not equal to 0. ENO has the same signal state as EN. 1 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 0 0 0 0 1 1 0 1 1 0 1 0 1 1 1 0 0 0 0 1 1 1 1 0 IN 31... ...16 15... ...0 3 places N OUT 1 0 1 1 The signal states of the three bits that are shifted out are inserted in the vacated places. Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: x x x x - x x x 1 Shift and Rotate Instructions 11.2 Rotate Instructions Ladder Logic (LAD) for S7-300 and S7-400 Programming 140 Reference Manual, 04/2017, A5E41524738-AA Example ROR_DW N IN EN MD0 MD10 Q 4.0 I 0.0 MW4 ENO OUT S The ROR_DW box is activated by logic "1" at I0.0. MD0 is loaded and rotated to the right by the number of bits specified with MW4. The result is written to MD10. Q4.0 is set. Ladder Logic (LAD) for S7-300 and S7-400 Programming Reference Manual, 04/2017, A5E41524738-AA 141 12 Status Bit Instructions 12.1 Overview of Statusbit Instructions Description The status bit instructions are bit logic instructions that work with the bits of the status word. Each of these instructions reacts to one of the following conditions that is indicated by one or more bits of the status word: • The Binary Result bit (BR ---I I---) is set (that is, has a signal state of 1). • A math function had an Overflow (OV ---I I---) or a Stored Overflow (OS ---I I---). • The result of a math function is unordered (UO ---I I---). • The result of a math function is related to 0 in one of the following ways: == 0, <> 0, > 0, < 0, >= 0, <= 0. When a status bit instruction is connected in series, it combines the result of its signal state check with the previous result of logic operation according to the And truth table. When a status bit instruction is connected in parallel, it combines its result with the previous RLO according to the Or truth table. Status word The status word is a register in the memory of your CPU that contains bits that you can reference in the address of bit and word logic instructions. Structure of the status word: BR CC1 CC0 OV OS OR STA RLO /FC 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 ...2 9 2 15 ... You can evaluate the bits in the status word • by Integer Math Functions, • by Floating-point Functions. Status Bit Instructions 12.2 OV ---| |--- Exception Bit Overflow Ladder Logic (LAD) for S7-300 and S7-400 Programming 142 Reference Manual, 04/2017, A5E41524738-AA 12.2 OV ---| |--- Exception Bit Overflow Symbol or negation / OV OV Description OV ---| |--- (Exception Bit Overflow) or OV ---| / |--- ( Negated Exception Bit Overflow) contact symbols are used to recognize an overflow in the last math function executed. This means that after the function executes, the result of the instruction is outside the permissible negative or positive range. Used in series, the result of the scan is linked to the RLO by AND, used in parallel, it is linked to the RLO by OR. Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: - - - - - x x x 1 Example SUB_I EN OUT IN2 ENO IN1 IW2 IW0 MW10 I 0.0 OV S Q 4.0 Network 1 Network 2 I 0.1 I 0.2 I 0.2 The box is activated by signal state "1" at I0.0. If the result of the math function "IW0 - IW2" is outside the permissible range for an integer, the OV bit is set. The signal state scan at OV is "1". Q4.0 is set if the scan of OV is signal state "1" and the RLO of network 2 is "1". Note The scan with OV is only necessary because of the two separate networks. Otherwise it is possible to take the ENO output of the math function that is "0" if the result is outside the permissible range. Status Bit Instructions 12.3 OS ---| |--- Exception Bit Overflow Stored Ladder Logic (LAD) for S7-300 and S7-400 Programming Reference Manual, 04/2017, A5E41524738-AA 143 12.3 OS ---| |--- Exception Bit Overflow Stored Symbol or negation / OS OS Description OS ---| |--- (Exception Bit Overflow Stored) or OS ---| / |--- (Negated Exception Bit Overflow Stored) contact symbols are used to recognize and store a latching overflow in a math function. If the result of the instruction lies outside the permissible negative or positive range, the OS bit in the status word is set. Unlike the OV bit, which is rewritten for subsequent math functions, the OS bit stores an overflow when it occurs. The OS bit remains set until the block is left. Used in series, the result of the scan is linked to the RLO by AND, used in parallel, it is linked to the RLO by OR. Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: - - - - - x x x 1 Example OS S Q 4.0 Network 1 Network 2 Network 3 ADD_I EN OUT IN2 ENO IN1 IW2 IW0 MW12 I 0.01 MUL_I EN OUT IN2 ENO IN1 IW2 IW0 MW10 I 0.0 Status Bit Instructions 12.3 OS ---| |--- Exception Bit Overflow Stored Ladder Logic (LAD) for S7-300 and S7-400 Programming 144 Reference Manual, 04/2017, A5E41524738-AA The MUL_I box is activated by signal state "1" at I0.0. The ADD_I box is activated by logic "1" at I0.1. If the result of one of the math functions was outside the permissible range for an integer, the OS bit in the status word is set to "1". Q4.0 is set if the scan of OS is logic "1". Note The scan with OS is only necessary because of the two separate networks. Otherwise it is possible to take the ENO output of the first math function and connect it with the EN input of the second (cascade arrangement). Status Bit Instructions 12.4 UO ---| |--- Exception Bit Unordered Ladder Logic (LAD) for S7-300 and S7-400 Programming Reference Manual, 04/2017, A5E41524738-AA 145 12.4 UO ---| |--- Exception Bit Unordered Symbol or negation / UO UO Description UO ---| |--- (Exception Bit Unordered) or UO ---| / |--- (Negated Exception Bit Unordered) contact symbols are used to recognize if the math function with floating-point numbers is unordered (meaning, whether one of the values in the math function is an invalid floating-point number). If the result of a math function with floating-point numbers (UO) is invalid, the signal state scan is "1". If the logic operation in CC 1 and CC 0 shows "not invalid", the result of the signal state scan is "0". Used in series, the result of the scan is linked to the RLO by AND, used in parallel it is linked to the RLO by OR. Status word BR CC 1 CC 0 OV OS OR STA RLO /FC writes: - - - - - x x x 1 Example UO S Q 4.1 DIV_R EN OUT IN2 ENO IN1 ID4 ID0 MD10 I 0.0 S Q 4.0 The box is activated by signal state "1" at I0.0. If the value of ID0 or ID4 is an invalid floating-point number, the math function is invalid. If the signal state of EN = 1 (activated) and if an error occurs during the processing of the function DIV_R, the signal state of ENO = 0. Output Q4.1 is set when the function DIV_R is executed but one of the values is not a valid floating-point number. Status Bit Instructions 12.5 BR ---| |--- Exception Bit Binary Result Ladder Logic (LAD) for S7-300 and S7-400 Programming 146 Reference Manual, 04/2017, A5E41524738-AA Yüklə 1,39 Mb. Dostları ilə paylaş:
|